LMK03000 National Semiconductor Corporation, LMK03000 Datasheet - Page 11

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LMK03000

Manufacturer Part Number
LMK03000
Description
Manufacturer
National Semiconductor Corporation
Datasheet

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2.0 General Programming Information
The LMK03000/LMK03000C/LMK03001/LMK03001C devices are programmed using several 32-bit registers which control the
device's operation. The registers consist of a data field and an address field. The last 4 register bits, ADDR[3:0] form the address
field. The remaining 28 bits form the data field DATA[27:0].
During programming LE is low, serial data is clocked in on the rising edge of clock (MSB first). When LE goes high, data is transferred
to the register bank selected by the address field. Only registers R0 to R7, R11, and R13 to R15 need to be programmed for proper
device operation.
For the frequency calibration algorithm to work properly OSCin must be driven by a valid signal when R15 is programmed.
2.1 RECOMMENDED PROGRAMMING SEQUENCE
The recommended programming sequence involves programming R0 with the reset bit set (RESET = 1) to ensure the device is
in a default state. It is not necessary to program R0 again, but if R0 is programmed again, the reset bit is programmed clear (RESET
= 0). Registers are programmed in order with R15 being the last register programmed. An example programming sequence is
shown below.
Any changes to the PLL R divider require R15 to be programmed again to active the frequency calibration routine.
R0 with the reset bit set (RESET = 1). This ensures the device is in a default state. When the reset bit is set in R0, the other
R0 bits are ignored.
— If R0 is programmed again, reset bit is programmed clear (RESET = 0).
R0 to R7 as necessary with desired channels with appropriate enable, mux, divider, and delay settings.
R11 with DIV4 setting if necessary.
R13 with oscillator input frequency and internal loop filter values
R14 with Fout enable bit, global clock output bit, power down setting, PLL mux setting, and PLL R divider.
R15 with PLL charge pump gain, input divider, and PLL N divider.
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