LMK03000 National Semiconductor Corporation, LMK03000 Datasheet - Page 14

• Manufacturer Part Number: LMK03000
• Manufacturer: National Semiconductor Corporation

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2.2 REGISTER R0 to R7
Registers R0 through R7 control the eight clock output pins. Register R0 controls CLKout0, Register R1 controls CLKout1, and so
on. There is one additional bit in register R0 called RESET. Aside from this, the functions of these bits are identical. The X in
CLKoutX_MUX, CLKoutX_DIV, CLKoutX_DLY, and CLKoutX_EN denote the actual clock output which may be from 0 to 7.
2.2.1 RESET bit -- R0 only
This bit is only in register R0. The use of this bit is optional and it should be set to '0' if not used. Setting this bit to a '1' forces all
registers to their power on reset condition. If this bit is set, all other R0 bits are ignored and R0 needs to be programmed again if
used with its proper values and RESET = 0.
2.2.2 CLKoutX_MUX[1:0] -- Clock Output Multiplexers
These bits control the Clock Output Multiplexer for each pin. Changing between the different modes changes the blocks in the
signal path and therefore incurs a delay relative to the bypass mode. The different MUX modes and associated delays are listed
below.
2.2.3 CLKoutX_DIV[7:0] -- Clock Output Dividers
These bits control the clock output divider value. In order for these dividers to be active, the respective CLKoutX_MUX (See 2.2.2)
bit must be set to either "Divided" or "Divided and Delayed" mode. After all the dividers are programed, the SYNC* pin must be
used to ensure that all edges of the clock output pins are aligned (See 1.7). The Clock Output Dividers follow the Input Divider so
the final clock divide for an output is Input Divider * Clock Output Divider. By adding the divider block to the output path a fixed
delay of approximately 100 ps is incurred.
The actual Clock Output Divide value is twice the binary value programmed as listed in the table below.
0
0
0
0
0
0
1
.
CLKoutX_MUX[1:0]
0
0
0
0
0
0
1
.
0
1
2
3
0
0
0
0
0
0
1
.
CLKoutX_DIV[7:0]
0
0
0
0
0
0
1
.
0
0
0
0
0
0
1
.
Divided and Delayed
Bypassed
Delayed
Divided
Mode
14
0
0
0
0
1
1
1
.
0
0
1
1
0
0
1
.
Added Delay Relative to Bypass Mode
0
1
0
1
0
1
1
.
(In addition to the programmed delay)
(In addition to the programmed delay)
Clock Output Divider value
100 ps
400 ps
500 ps
0 ps
Invalid
510
10
...
2
4
6
8