LMK03000 National Semiconductor Corporation, LMK03000 Datasheet - Page 15

• Manufacturer Part Number: LMK03000
• Manufacturer: National Semiconductor Corporation

2.2.4 CLKoutX_DLY[3:0] -- Clock Output Delays
These bits control the delay stages for each clock output pin. In order for these delays to be active, the respective CLKoutX_MUX
(See 2.2.2) bit must be set to either "Delayed" or "Divided and Delayed" mode. By adding the delay block to the output path a fixed
delay of approximately 400 ps is incurred in addition to the delay shown in the table below.
2.2.5 CLKoutX_EN bit -- Clock Output Enables
These bits control whether an individual clock output is enabled or not. If the EN_CLKout_Global bit (See 2.5.4) is set to zero or if
GOE pin is held low, all CLKoutX_EN bit states will be ignored and all clock outputs will be disabled. See 1.8 for more information
on CLKout states.
2.3 REGISTER R11
This register only has one bit and only needs to be programmed in the case that the OSCin frequency is greater than 20 MHz and
digital lock detect is used. Otherwise, it is automatically defaulted to the correct values.
2.3.1 DIV4
This bit divides the frequency presented to the digital lock detect circuitry by 4. It is necessary to get a reliable output from the
digital lock detect output in the case of a OSCin frequency greater than 20 MHz.
CLKoutX_EN bit
0
1
CLKoutX_DLY[3:0]
0 (Default)
DIV4
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
1
EN_CLKout_Global bit
1
1
15
Frequency Presented to the Digital Lock Detect Circuitry
GOE pin
0
0
Divided by 4
Not divided
Delay (ps)
1050
1200
1350
1500
1650
1800
1950
2100
2250
150
300
450
600
750
900
0
CLKoutX State
Disabled
Enabled
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