hy27uh084g2m Hynix Semiconductor, hy27uh084g2m Datasheet - Page 15

• Manufacturer Part Number: hy27uh084g2m
• Description: 4gbit 512mx8bit / 256mx16bit Nand Flash
• Manufacturer: Hynix Semiconductor

3.9 Cache Read
Cache read operation allows automatic download of consecutive pages, up to the whole device. Immediately after 1st
latency end, while user can start reading out data, device internally starts reading following page.
Start address of 1st page is at page start (A<10:0>=00h), after 1st latency time (tr) , automatic data download will
be uninterrupted. In fact latency time is 27us, while download of a page require at least 100us for x8 device (50us for
x16 device).
Cache read operation command is like standard read, except for confirm code (30h for standard read, 31h for cache
read) user can check operation status using :
To exit cache read operation a cache read exit command (34h) must be issued. this command can be given any time
(both device idle and reading).
If device is active (SR<5>=0) it will go idle within 5us, while if it is not active, device itself will go busy for a time
shorter then tCBSY before becoming again idle and ready to accept any further commands.
If user arrives reading last byte/word of the memory array, then has to stop by giving a cache read exit command.
Random data output is not available in cache read.
Cache read operation must be done only block by block if system needs to avoid reading also from invalid blocks.
Rev 0.7 / Nov. 2005
- RB# ( ‘0’ means latency ongoing, download not possible, ‘1’ means download of n page possible, even if device
- Status register (SR<6> behave like RB#, SR<5> is ‘0’ when device is internally reading and ‘1’ when device is idle)
internally is active on n+1 page
4Gbit (512Mx8bit / 256Mx16bit) NAND Flash
HY27UH(08/16)4G2M Series
HY27SH(08/16)4G2M Series
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