hsp50216 Intersil Corporation, hsp50216 Datasheet - Page 26

• Manufacturer Part Number: hsp50216
• Description: Four-channel Programmable Digital Downconverter
• Manufacturer: Intersil Corporation

The enable signal for gating data into the coordinate
converter is either the AGC data ready signal or the
resampler data ready signal. If the resampler is bypassed,
the AGC data ready signal is used and there is a delay of 6
clock cycles between the FIR data being ready and the
coordinate converter block sampling it. If the resampler is
enabled, its data ready signal will be delayed by 6 clocks (for
the AGC) plus the compute delay of the resampler block.
This may cause the I/Q to |r|/θ output sample alignment to
shift with the decimation. For this reason, it is recommended
that the resampler/halfband filter block be bypassed when
using this new data path.
†
Assumes ±180° = f
CLOCKS
TABLE 2. MAG/PHASE ACCURACY vs CLOCK CYCLES
10
11
12
13
14
15
16
17
6
7
8
9
MAGNITUDE
ERROR
<0.004
<0.004
<0.004
<0.004
<0.004
<0.004
<0.004
<0.004
<0.004
(% f
S
0.065
0.016
0.004
.
S
)
26
ERROR
0.00175
PHASE
(DEG.)
0.0035
0.056
0.028
0.014
0.007
0.45
0.22
0.11
3.5
1.8
0.9
†
ERROR
PHASE
(% f
0.062
0.016
0.008
0.004
0.002
0.001
0.25
0.12
0.03
0.5
2
1
S
)
HSP50216
August 17, 2007
FN4557.6