hsp50215 Intersil Corporation, hsp50215 Datasheet - Page 21
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hsp50215
Manufacturer Part Number
hsp50215
Description
Digital Upconverter
Manufacturer
Intersil Corporation
Datasheet
1.HSP50215.pdf
(21 pages)
Waveforms
NOTE: CASZ, OFM, OE are signals that must remain constant with
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out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
WR OR-ED CE
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REFCLK
FIGURE 17. TIMING RELATIVE TO WR OR WITH CE
respect to REFCLK until the part is reset. In the write mode,
either CE or WR must be clocked while the other is tied low.
In read mode, either CE or RD must be clocked while the oth-
er is tied low. Never tie all three interface signals (CE, RD and
WR) low at the same time.
SAMPCLK, SYNCOUT,
CAS(15:0),
FIFORDY
FIGURE 19. TIMING RELATIVE TO REFCLK
SYNCIN
C15-0
A9-0
OUT(15:0)
FIFORDY
t
WRL
t
DS
3-442
t
CL
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t
t
AS
CS
t
CP
t
WF
t
CH
t
DH
t
t
DOC
DO
t
t
AH
CH
t
WRH
HSP50215
RD OR’ed CE
C15-0
A9-0
OUT(15:0)
FIGURE 21. TIMING RELATIVE TO READ OR TO CE
t
OE
RDO
FIGURE 18. OUTPUT RISE AND FALL TIMES
0.8V
FIGURE 20. OUTPUT ENABLE/DISABLE
2.0V
t
RF
t
OE
t
RL
1.5V
1.7V
1.3V
t
ROD
1.5V
t
t
RF
ADO
t
OD