hsp50214a Intersil Corporation, hsp50214a Datasheet - Page 55

• Manufacturer Part Number: hsp50214a
• Description: Programmable Downconverter
• Manufacturer: Intersil Corporation

CONTROL WORD 25: COUNTER AND ACCUMULATOR RESET (SYNCHRONIZED TO BOTH CLKIN AND PROCCLK) (Continued)
POSITION
POSITION
POSITION
19 - 18
31-25
12-0
N/A
BIT
BIT
BIT
24
24
23
22
21
20
17
16
15
14
13
Test Circuit Disable
AGC Load
Reserved
RAM Test Enable
Input Level Detector
Counter Preload
Select
SYNCIN1 Reset
Control
Timing Error Input
Select
Timing NCO Reset
Control Select
Discriminator FIR
Input
Input Level Detector
Integration Start
Select
AGC Average
Control
AGC Clear Inhibit
Q Input to Coordi-
nate Converter (see
bits 19 - 15)
Coordinate Convert-
er Input
Reserved
FUNCTION
FUNCTION
FUNCTION
CONTROL WORD 26: LOAD AGC GAIN (SYNCHRONIZED TO PROCCLK)
CONTROL WORD 27: TEST REGISTER (SYNCHRONIZED TO CLKIN)
The A Version includes test circuitry for the ROM and RAM blocks that was not present in the orig-
inal release part. This circuitry must be disabled before loading the coefficient RAM’s. This is done
by setting bit 24 to zero.
NOTE: Because the HSP50214 did not require a “write” to Control Word 25 and the
Writing to this location generates a strobe to load the AGC loop accumulator with bits (15:5) to
the master registers. These bits are loaded into the MSBs of the AGC loop filter accumulator
with bits (15:12) mapping to the shift (exponent) control bits and bits (11:5) mapping to the mul-
tiplier (mantissa) bits. Bits (11:5) represent a binary mantissa mapped to the linear gain as:
01.XXXXXXX. See AGC Section.
A fixed value of 0000 000 is loaded here for normal operation.
0 = Normal Operation; 1 = RAM Test Enabled.
0 = The two LSB’s of the interpolation period preload are set to zero.
1 = The two LSB’s of the interpolation period preload are set to one.
0: SYNCIN1 causes only front end reset.
1: SYNCIN1 causes front end and back end resets.
0 = Operates as HSP50214.
1 = Corrects an error in the 4 LSB’s.
0 = Backend reset will not clear the timing NCO phase accumulator feedback.
1 = Backend reset clears the timing NCO phase accumulator.
00 = 18 bits of delayed and subtracted (optionally shifted) phase.
01 = 18 bits of magnitude from coordinate converter.
1X = 18 bits of resampler/halfband filer I output.
0 = No external sync control of input end detector start/restart of integration period.
1 = SYNCIN causes the input level detector to start/restart its integration period.
0: AGC settles to mean.
1: AGC settles to median.
When set to zero, this bit will clear the AGC loop filter accumulator on a SYNCIN2 assertion or
a WRITE to CW 25.
When set to a one, a WRITE to CW25 will not clear the AGC loop filter accumulator.
0 = I and Q enabled to coordinate converter.
I = Q input to coordinate converter is zeroed.
0 = The Resampler HB filter output is routed to coordinate converter.
1 = The output of 255 tap FIR is routed to coordinate converter.
A fixed value 0 0010 0111 1000 [0278]hex is loaded here for normal operation.
A fixed value 0 0010 0111 1010 [027A]hex is loaded here for setting the Sin/Cos Generator out-
puts to 7FFF.
HSP50214A does require that Control Word 25, Bit 24 be set to zero for normal
operation, software that was written for the HSP50214 will require modification to
work properly with the HSP50214A.
HSP50214A
55
DESCRIPTION
DESCRIPTION
DESCRIPTION