ipm6210a Intersil Corporation, ipm6210a Datasheet - Page 9

• Manufacturer Part Number: ipm6210a
• Description: Precision Dual Pwm Controller And Linear Regulator For Notebook Cpus
• Manufacturer: Intersil Corporation

This leads to deterioration of the droop benefits in the
battery-optimized mode where they are mostly appreciable,
Figure 2.
The IPM6210A incorporates a new proprietary droop
technique specially designed for the SpeedStep
converters and provides mode-compensated, relatively
equal droop in both, the performance and the battery-
optimized modes. The droop is set as a fraction of the VID
programmed voltage and the gain in the current loop is
different for each VID combination. That makes the droop
compensated for the voltage and the frequency changes
associated with the different CPU modes of operation.
To accommodate the droop the output voltage of core
converter is raised 2% at no load conditions. The resistor
connected to ISEN1 pin programs the amount of droop.
R
1
2
1
2
C S
Ch1 50mV
=
Ch1 50mV
I
--------------------------------------- -
MAX
75µA
xr
DS ON
(
V
V
CPU
CPU
)
Ch2 5.0A
–
Ch2 5.0A
= 1.6V
I
100Ω
CPU
= 1.35V
I
CPU
FIGURE 3.
FIGURE 4.
= 0.3A>>18A
= 0.3A>>13.5A
9
M50µs
M50ms
TM
- enabled
IPM6210A
This resistor sets the gain in the current feedback loop. The
droop is scaled to 5.5% of the VID code when current into
ISEN1 pin equals 75µA.
The output voltage waveforms with droop subjected to load
step are shown on Figures 3 through 5.
Feedback Loop Compensation
Due to implemented average current mode control, the
modulator has a single pole response with -1 slope at
frequency determined by load:
F
where R
this type of modulator Type 2 compensation circuit is usually
sufficient. To reduce number of external components and
remove the burden at determining compensation
components from a system designer, both PWM controllers
have internally compensated error amplifiers.
Figure 6 shows Type 2 amplifier and its response along with
responses of current mode modulator and the converter. The
Type 2 amplifier, in addition to the pole at origin, has a
zero-pole pair that causes a flat gain region at frequencies in
between the zero and the pole.
F
F
This region is also associated with phase ‘bump’ or reduced
phase shift. The amount of phase shift reduction depends on
how wide the region of flat gain is and has a maximum value
of 90 degrees. To further simplify the converter
compensation, the modulator gain is kept independent of the
input voltage variation by providing feed-forward of V
the oscillator ramp.
1
2
PO
Z
P
=
=
=
Ch1 50mV
-----------------------------
2πxR
-----------------------------
2πxR
------------------------------- -
2πxR
O
1
1
is load resistance; C
2
1
xC
1
xC
O
xC
1
2
O
=
=
,
V
6kHz
600k Hz
CPU
Ch2 5.0A
= 1.00V
I
CPU
;
FIGURE 5.
;
= 0.3A>>12.0A
O
is load capacitance. For
M50ms
IN
to