ak4528 AKM Semiconductor, Inc., ak4528 Datasheet - Page 16

• Manufacturer Part Number: ak4528
• Description: High Performance 24bit 96khz Audio Codec
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
The ADC and DAC of AK4528 are placed in the power-down mode by bringing a power down pin (PDN)=“L” and each
digital filter is also reset at the same time. The internal register values are initialized by PDN = “L”. This reset should
always be done after power-up.
In case of serial mode, the default value of both control registers for ADC and DAC are in reset state (RSTADN =
RSTDAN = “0”), each register sholud be cancelled after doing the needed setting. In case of the ADC, an analog
initialization cycle starts after exiting the power-down or reset state. Therefore, the output data, SDTO becomes available
after 516 cycles of LRCK. In case of DAC, the initialization cycle starts after PDN = “H” or PWVR bit = “1”. The power
down mode can be also controlled by the registers (PWAD, PWDA).
MS0011-E-01
Power Supply
PDN pin
RSTADN(registe
RSTDAN(registe
PWAD(register)
PWDA(register)
PWVR(register)
ADC Internal State
SDTO
DAC Internal State
OATT
AOUT
External Mute
Example
External clocks
Power Down & Reset
• INITA:
• INITD:
• PD:
hold.
• XXH:
• FI:
• AOUT:
Initializing period of ADC analog section (516/fs).
Initializing period of DAC analog section (512/fs).
The current value in ATT register.
Fade in. After exiting power down and reset state, ATT value fades in by 8032/fs cycles (max).
Some pop noise may occur at “*”.
PD
PD
Power down state. In case of PDN = “L”, the contents of all registers are initialized, otherwise
Hi-Z
Reset INITA
INITD
“0”
The clocks can be stopped.
00H
*
Figure 7. Reset & Power down sequence in Serial Mode
512/fs
Reset
“0”
MCLK, LRCK, BICK
*
00H → XXH
Normal
Output
FI
Normal
PD
- 16 -
Output
XXH
“0”
INITA
*
00H
Hi-Z
PD
*
Normal
Output
00H → XXH
Normal
FI
XXH
Output
*
00H
PD
Hi-Z
INITD
00H → XXH
*
PD
“0”
512/fs
FI
Normal
[AK4528]
2004/01
Output
XXH