ak4522 AKM Semiconductor, Inc., ak4522 Datasheet - Page 9

• Manufacturer Part Number: ak4522
• Description: 20bit Stereo ?? Adc & Dac
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
n System Clock
The master clock (MCLK) can be external clock input to the MCKI pin. CMODE is used to select either MCLK=256fs,
384fs or 512fs. The relationship between the MCLK and the desired sample rate is defined in Table 1. The LRCK clock
input must be synchronized with MCLK, however the phase is not critical. Internal timing is synchronized to LRCK upon
power-up. All external clocks must be present unless PD = “L”, otherwise excessive current may result from abnormal
operation of internal dynamic logic.
n Audio Serial Interface Format
Data is shifted in/out the SDTI/SDTO pins using SCLK and LRCK inputs. Four serial data modes selected by the DIF0
and DIF1 pins are supported as shown in Table 2. In all modes the serial data has MSB first, 2’s compliment format. The
data is clocked out on the falling edge of SCLK and latched on the rising edge. For mode 3, if SCLK is 32fs, then the least
significant bits will be truncated.
M0020-E-01
SCLK(i:32fs)
SDTO(o)
SDTI(i)
SCLK(i:64fs)
SDTO(o)
SDTI(i)
LRCK(i)
Mode
32.0kHz
44.1kHz
48.0kHz
0
1
2
3
fs
DIF1
0
0
0
0
1
1
SDTO-19:MSB, 0:LSB; SDTI-15:MSB, 0:LSB
19
15 14 13
19
256fs
CMODE=”L”
Don’t Care
1
1
11.2896MHz
12.2880MHz
8.1920MHz
18
18
2
2
17
17
DIF0
3
3
0
1
0
1
11 10
15
7
3
17
Lch Data
9
14
2
6
384fs
CMODE=”H”
20bit, MSB justified
20bit, MSB justified
20bit, MSB justified
10
18
16.9344MHz
18.4320MHz
12.2880MHz
13
9
5
1
SDTO (ADC)
Table 1. System Clock Example
11
19
MCLK
OPERATION OVERVIEW
IIS (I2S)
12 11
Table 2. Serial Data Modes
0
4
8
Figure 1. Mode 0 Timing
12
20
7
3
13
6
2
2
14
30
- 9 -
1
1
5
512fs
CMODE=”NC”
15
31
4
0
0
16.384MHz
22.579MHz
24.576MHz
0
0
20bit, MSB justified
16bit, LSB justified
20bit, LSB justified
19 18
15
19 18
Don’t Care
1
1
SDTI (DAC)
14 13
IIS (I2S)
2
2
17
17
3
15
11 10
7
3
2.048MHz
2.822MHz
3.072MHz
17
Rch Data
9
14
6
2
64fs
10
18
13
5
1
9
11
19
L/R
H/L
H/L
H/L
L/H
12 11
4
0
8
SCLK
12
20
7
3
13
6
2
2
14
5.644MHz
6.144MHz
4.096MHz
32fs or 40fs
5
1
1
128fs
SCLK
15
31
32fs
40fs
40fs
[AK4522]
4
0
0
1998/10
0
0
19
15
19
1
1