ak4555 AKM Semiconductor, Inc., ak4555 Datasheet - Page 11

• Manufacturer Part Number: ak4555
• Description: Low Power & Small Package 20bit ?? Codec
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
The ADC and DAC of AK4555 are placed in the power-down mode by bringing each power down pin, PWADN,
PWDAN = “L” independently and each digital filter is also reset at the same time. These resets should always be done
after power-up. In case of the ADC, an anlog initialization cycle starts after exiting the power-down mode. Therefore, the
output data, SDTO becomes available after 2081 cycles of LRCK clock. This initialization cycle does not affect the DAC
operation. Figure 5 shows the power-up sequence when the ADC is powered up before the DAC power-up.
MS0363-E-01
Power-down & Reset
Clock In
MCLK,LRCK,SCLK
DAC Internal
DAC In
DAC Out
ADC Internal
ADC In
ADC Out
External
PWADN
PWDAN
(Digital)
(Analog)
(Analog)
(Digital)
Mute
State
State
Normal Operation
Normal Operation
Idle Noise
GD
GD
Figure 5. Power-up Sequence
Power-down
Mute ON
Power-down
The clocks may be stopped.
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“0”data
“0”data
Normal Operation
Init Cycle
2081/fs
GD
Idle Noise
Normal Operation
GD
[AK4555]
2005/08