ak4586 AKM Semiconductor, Inc., ak4586 Datasheet
ak4586
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ak4586 Summary of contents
Page 1
... Control may be set directly by programmed through a separate serial interface. The AK4586 has a dynamic range of 100dB for ADC, 106dB for DAC and is well suited for digital surround for home theater and car audio. The AK4586 also has the balance volume control corresponding to the AC-3 system ...
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... HPF I/F HPF MCLK Clock Recovery DATT DAIF Decoder DATT DEM DATT DATT SDOUT BICK LRCK DATT SDIN1 SDIN2 SDIN3 DATT - 2 - [AK4586 TDM XTI X’tal Oscillator XTO Clock MCKO Generator TX RX1 Input RX2 RX3 Selector RX4 SDTO BICK LRCK SDTI1 SDTI2 ...
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... ASAHI KASEI Ordering Guide AK4586VQ AKD4586 Pin Layout XTO XTI/EXTCLK DVDD DVSS TVDD TX MCKO LRCK BICK SDTO SDTI1 MS0097-E-01 -40 +85 C 44pin LQFP(0.8mm pitch) Evaluation Board for AK4586 AK4586VQ 6 7 Top View [AK4586] 33 RIN 32 LIN 31 ROUT1 30 LOUT1 ...
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... Not available Available Available Not available CMOS - 4 - [AK4586] AK4586 90dB 100dB 6ch Available Not available Available fixed to “00” AK4586 4.5 5.5V 32k 96kHz 1 pin 256fs/384fs/512fs for Normal speed 128fs/192fs/256fs for Double speed 2 pins Available Not available Not available Available TTL 2001/12 ...
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... This pin goes to “H” if the analog input of Lch or Rch is overflows. 21 AVSS - Analog Ground Pin AVDD - Analog Power Supply Pin, 4.5V 5.5V MS0097-E-01 PIN/FUNCTION Function 2 C bus control mode 2 C bus control mode 2 C bus control mode 2 C bus control mode (Note [AK4586] 2001/12 ...
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... PDN I Power-Down & Reset Pin When “L”, the AK4586 is powered-down, all output pins go to “L” and the control registers are reset to default state. If the state of CAD1-0 changes, then the AK4586 must be reset by PDN. Notes: 1. The group 1 and 2 can be selected by DZFM2-0 bits. ...
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... ABSOLUTE MAXIMUM RATINGS Symbol min AVDD -0.3 DVDD -0.3 PVDD -0.3 TVDD -0.3 (Note 5) - GND1 (Note 5) - GND2 IIN - VINA -0.3 VIND1 -0.3 VIND2 -0.3 VIND3 -0.3 Ta -40 Tstg -65 Symbol min AVDD 4.5 DVDD 4.5 PVDD 4.5 TVDD 2 [AK4586] max Units 6.0 V 6.0 V 6.0 V 6.0 V 0 AVDD+0.3 V DVDD+0.3 V TVDD+0.3 V PVDD+0 150 C typ max Units 5.0 5.5 V 5.0 5.5 V 5.0 5.5 V 5.0 5 ...
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... LRCK) are held DVSS. MS0097-E-01 ANALOG CHARACTERISTICS min AIN=0.62xVREFH 2.90 AIN=0.65xVREFH 3.05 (Note 8) 15 (Note 2.75 5 (Note 9) (Note 11) (Note 12) (Note 13 [AK4586] typ max Units 24 Bits 100 dB 100 dB 100 dB 100 dB 110 dB 0.2 0 ppm/ C 3.10 3.30 Vpp 3.25 3.45 Vpp ...
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... VIH 2.2 VIH 70%DVDD VIL - VIL - (Note 17) VAC 40%DVDD VOH TVDD-0.5 VOH Iout=-400µA) DVDD-0.5 VOH Iout=-400µA) AVDD-0.5 VOL Iout= 400µA) - VOL Iout= 3mA) - Iin - - 9 - [AK4586] typ max Units 18.9 kHz 20.0 - kHz 23.0 - kHz kHz dB 0.1 dB 17.0 1/fs 0 µs 1.0 Hz 6.5 Hz 21.8 kHz 24.0 - kHz ...
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... Duty 45 fsn 32 tLRH 1/256fs tLRL 1/256fs fsn 32 (Note 19) tLRH =15pF when MCKO is above 22.5792MHz [AK4586] typ max Units 24.576 MHz 12.288 MHz ns ns 18.432 MHz ns ns 24.576 MHz ns ns 24.576 MHz kHz 48 kHz ...
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... Units 64fs ...
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... PDN “ ” to SDTO valid Notes: 22. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. 23. The AK4586 can be reset by bringing PDN “L” to “H” upon power-up. 24. These cycles are the number of LRCK rising from PDN rising registered trademark of Philips Semiconductors ...
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... Clock Timing (TDM= “0”) 1/fCLK tCLKH tCLKL 1/fs tLRH tLRL tBCK tBCKH tBCKL Clock Timing (TDM= “1” [AK4586] VIH VIL 50%TVDD = tMCKL x fMCK x 100 VIH VIL = tLRL 100 VIH VIL VIH VIL VIH VIL VIH VIL ...
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... Audio Interface Timing (Slave mode, TDM= “1”) LRCK tMBLR BICK SDTO SDTI MS0097-E-01 tLRB tSDS tSDH tLRB tSDS tSDH tSDS tSDH Audio Interface Timing (Master Mode [AK4586] VIH VIL VIH VIL tBSD 50%TVDD VIH VIL VIH VIL VIH VIL tBSD 50%TVDD VIH VIL ...
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... READ Data Output Timing 1 (4-wire serial mode) MS0097-E-01 tCSS tCCKL tCCKH tCDH tCDS C1 C0 R/W Hi-Z tCSW tCSH Hi-Z A0 tDCD [AK4586] VIH VIL VIH VIL VIH A4 VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL 50%TVDD D5 2001/12 ...
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... Start tPD PDN SDTO MS0097-E-01 tCSW tCSH tHIGH tF tSU:DAT tSU:STA Start Bus mode Timing tPDV Power-down & Reset Timing - 16 - [AK4586] VIH VIL VIH VIL VIH VIL tCCZ 50%TVDD VIH VIL tSP VIH VIL tSU:STO Stop VIH VIL 50%TVDD 2001/12 ...
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... DTS-CD stream auto detect function. When the AK4586 detects the DTS-CD bitstreams, the DTSCD bit goes to “1”. When the next sync code does not come within 4096 flames, the DTSCD bit goes to “0” until the AK4586 detects the stream again ...
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... Double Speed Mode ICKS0 Normal Double 0 0 256fs 128fs 0 1 384fs 192fs 1 0 512fs 256fs 1 1 256fs 256fs CLKDIV MCKO 0 XTI x1 Default 1 XTI x1/2 x1/2 CLKDIV CM1-0 OCKS1-0 Figure 1. Master Clock Output Select - 18 - [AK4586] 44.1kHz~48kHz 88.2kHz~96kHz 32kHz~48kHz 88.2kHz~96kHz 32kHz~48kHz 88.2kHz~96kHz Default MCKO 2001/12 ...
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... ASAHI KASEI Clock Source The following circuits are available to feed the clock to XTI pin of AK4586. 1) X’tal Note: External capacitance depends on the crystal oscillator (Typ. 10-40pF) 2) External clock External Clock(5V) External Clock(3.3V) Note: 3.3V external clock should be AC coupled. The amplitude of the clock should be larger than 40%DVDD. ...
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... ASAHI KASEI Sampling Frequency and Pre-emphasis Detect The AK4586 outputs the encoded information of sampling frequency and pre-emphasis in channel status to FS0, FS1 and PEM bits in control register. These information are output from channel 1 at default. It can be switched to channel 2 by CS12 bit in control register. ...
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... System Reset and Power-Down The AK4586 has a power-down mode for all circuits by PDN pin or can be partially powered-down by internal register. The AK4586 should be reset once by bringing PDN pin = “L” upon power-up. ADC, DAC and PLL are powered-down at PWVRN= “0”. PDN ...
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... Table 12). The TX output can be stopped by setting TXE bit “0”. IPS1 OPS1 MS0097-E-01 IPS0 INPUT Data 0 RX1 Default 1 RX2 0 RX3 1 RX4 Table 11. Recovery data select OPS0 INPUT Data 0 RX1 Default 1 RX2 0 RX3 1 RX4 Table 12. Output data select - 22 - [AK4586] 2001/12 ...
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... In case of coaxial input, as the input level of RX line is small, be careful not to crosstalk among RX input lines. For example, by inserting the shield pattern among them. The AK4586 includes the TX output buffer. The output level meets combination 0.5V+/-20% using the external resistor network. The T1 in Figure transformer of 1:1. ...
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... EFH1-0 bits) after the all factors are removed. Once the PAR bit goes to “1”, it holds “1” until reading the register. While the AK4586 loses lock, the channel status bits are not updated and hold the previous data. At initial state, INT0 outputs the ORed signal between UNLOCK and PAR. INT1 outputs the ORed signal among AUTO, DTSCD, AUDION and V. INT1-0 pins are “ ...
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... Command MCKO,BICK,LRCK (UNLOCK) MCKO,BICK,LRCK (except UNLOCK) SDTO (UNLOCK) SDTO (PAR error) SDTO (others) MS0097-E-01 (Error) Hold Time (max: 4096/fs) Hold Time = 0 Hold ”1” READ 0EH Free Run (fs: around 20kHz) Previous Data Figure 9. INT0/1 pin timing - 25 - [AK4586] Reset Normal Operation 2001/12 ...
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... ASAHI KASEI Release Muting Figure 10. Error Handling Sequence Example MS0097-E-01 PDN pin ="L" to "H" Initialize Read 0EH INT0/1 pin ="H" No Yes Mute DAC output Read 0EH (Each Error Handling) No INT0/1 pin ="H" Yes - 26 - [AK4586] 2001/12 ...
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... Eight serial data formats can be selected by the DIF2-0 bits as shown in Table 14 at the SLAVE pin “L”. If the SLAVE pin is “H”, the AK4586 is fixed in the slave mode and two serial data format can be selected by the DIF0 bit. In all formats the serial data is MSB-first, 2's compliment format ...
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... Lch Data Figure 12. Mode 0 Timing Lch Data Figure 13. Mode 3 Timing - 28 - [AK4586] LRCK BICK I/O I/O O 256fs O O 256fs O O 256fs O O 256fs O O 256fs O O 256fs O I 256fs I I 256fs I I 256fs ...
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... Mode 4: LRCK, BICK: Output Mode 6: LRCK, BICK: Input Lch Data Figure 15. Mode 5, 7 Timing Mode 5: LRCK, BICK: Output Mode 7: LRCK, BICK: Input - 29 - [AK4586 Rch Data ...
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... BICK 32 BICK 32 BICK 32 BICK 32 BICK Figure 16. Mode 8 Timing 256 BICK Rch 32 BICK BICK 32 BICK 32 BICK 32 BICK 32 BICK Figure 17. Mode 11 Timing - 30 - [AK4586 BICK BICK 2001/12 ...
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... Mode 14: LRCK, BICK: Input 256 BICK 23 0 Rch 32 BICK BICK 32 BICK 32 BICK 32 BICK 32 BICK Figure 19. Mode 13, 15 Timing Mode 13: LRCK, BICK: Output Mode 15: LRCK, BICK: Input - 31 - [AK4586 BICK BICK 2001/12 ...
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... Overflow Detection The AK4586 has overflow detect function for analog input. Overflow detect function is enable if OVFE bit is set to “1”. OVF pin goes to “H” if analog input of Lch or Rch overflows (more than -0.3dBFS). OVF output for overflowed analog input has the same group delay as ADC (GD = 17.0/fs = 354µ ...
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... ASAHI KASEI Digital Attenuator The AK4586 has channel-independent digital attenuator (256 levels, 0.5dB step). Attenuation level of each channel can be set by each ATT7-0 bits (Table 17). ATT7-0 Table 17. Attenuation level of digital attenuator Transition time between set values of ATT7-0 bits can be selected by ATS1-0 bits (Table 18). ...
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... When the input data of all channels in the group are continuously zeros for 8192 LRCK cycles, DZF pin corresponding to the group goes to “H”. DZF pin immediately goes to “L” if input data of any channel in the group is not zero after going DZF “H”. MS0097-E-01 1024/fs (1) GD (2) (4) 8192/fs Figure 20. Soft mute and zero detection - 34 - [AK4586] (3) GD 2001/12 ...
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... Figure 21. 4-wire Serial Control I/F Timing MS0097-E- R Hi C1-0: Chip Address (Fixed to “00”) R/W: READ/WRITE (0:READ, 1:WRITE) A4-A0: Register Address D7-D0: Control Data - 35 - [AK4586 Hi 2001/12 ...
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... A “0” indicates that the write operation executed. The second byte consists of the address for control registers of the AK4586. The format is MSB first, and those most significant 3-bits are fixed to zeros (Figure 24). Those data after the second byte contain control data. The format is MSB first, 8bits (Figure 25) ...
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... READ Operations Set R/W bit = “1” for the READ operation of the AK4586. After transmission of a data, the master can read next address’s data by generating the acknowledge instead of terminating the write cycle after the receipt the first data word. After the receipt of each data, the internal 5bits address counter is incremented by one, and the next data is taken into next address automatically. If the address exceed 1FH prior to generating the stop condition, the address counter will “ ...
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... MASTER S START CONDITION SDA SCL MS0097-E-01 Figure 28. START and STOP conditions Figure 29. Acknowledge on the I C-bus data line change stable; of data data valid allowed 2 Figure 30. Bit transfer on the I C-bus - 38 - [AK4586] P stop condition not acknowledge acknowledge 8 9 clock pulse for acknowledgement 2001/12 ...
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... C20 C31 C30 C29 C28 PC7 DTSCD PC5 PC4 PC15 PC14 PC13 PC12 PD7 PD6 PD5 PD4 PD15 PD14 PD13 PD12 - 39 - [AK4586 PWVRN PWADN PWDAN IPS1 IPS0 OPS1 ICKS1 ICKS0 CM1 OVFE DZFM2 DZFM1 DZFM0 EFH0 DEAU DEM1 TDM DIF2 ...
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... LOOP1-0 should be set to “00” at TDM bit “1”. MS0097-E- PWVRN R LOOP1 LOOP0 RD RD R/W R [AK4586 PWADN PWDAN RSTN R/W R/W R IPS1 IPS0 OPS1 OPS0 R/W R/W R/W R 2001/12 ...
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... Default: “00”, mode 0 CLKDIV: Master Clock Output Select at X’tal mode (Table 5) 0: Same frequency as crystal oscillator 1: Half frequency of crystal oscillator MS0097-E- CLKDIV OCKS1 OCKS0 RD R/W R/W R [AK4586 ICKS1 ICKS0 CM1 CM0 R/W R/W R/W R 2001/12 ...
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... SMUTE: Soft Mute Enable (Figure 20) 0: Normal operation 1: All DAC outputs soft-muted MS0097-E- SMUTE TXE BCU RD R/W R/W R C(L0) C(R0) C(L1) 1/4fs R0 R191 L0 L0 L191 R191 - 42 - [AK4586 OVFE DZFM2 DZFM1 DZFM0 R/W R/W R/W R C(L31) C(R31) C(L32) R31 R30 L31 L31 L30 R30 2001/12 ...
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... ATS1-0: Digital attenuator transition time setting (Table 18) Default: “00”, mode 0 MS0097-E- XFS96 AFS96 CS12 EFH1 R/W R/W R/W R ATS1 ATS0 RD RD R/W R [AK4586 EFH0 DEAU DEM1 DEM0 R/W R/W R/W R TDM DIF2 DIF1 DIF0 R/W R/W R/W R 2001/12 ...
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... ATT7 ATT6 ATT5 ATT4 ATT7 ATT6 ATT5 ATT4 ATT7 ATT6 ATT5 ATT4 ATT7 ATT6 ATT5 ATT4 R/W R/W R/W R [AK4586 ATT3 ATT2 ATT1 ATT0 ATT3 ATT2 ATT1 ATT0 ATT3 ATT2 ATT1 ATT0 ATT3 ATT2 ATT1 ATT0 ATT3 ATT2 ATT1 ATT0 ...
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... MRFS1: Mask Enable for RFS96 bit (Default Mask disable 1: Mask enable MS0097-E- MV0 MSTC0 MAUD0 MDTS0 R/W R/W R/W R MV1 MSTC1 MAUD1 MDTS1 R/W R/W R/W R [AK4586 MAUT0 MPAR0 MUNL0 R/W R/W R MAUT1 MPAR1 MUNL1 R/W R/W R 2001/12 ...
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... AUDION DTSCD Unlock 1: Error 1: Detect 1: Detect 1: Non audio 1: Detect 1: Invalid 1: fs=88.2kHz or more [AK4586 AUTO PAR UNLOCK PEM FS1 FS0 2001/12 ...
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... RD Not initialized PC7 PC6 PC5 PC4 PC15 PC14 PC13 PC12 PD7 PD6 PD5 PD4 PD15 PD14 PD13 PD12 RD Not initialized - 47 - [AK4586 C11 C10 C9 C8 C19 C18 C17 C16 C27 C26 C25 C24 PC3 ...
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... LSB 16 bits of bitstream 0 Burst_payload repetition time of the burst Figure 31. Data structure in IEC60958 Contents Value sync word 1 0xF872 sync word 2 0x4E1F Burst info see Table 20 Length code numbers of bits Table 19. Burst preamble words - 48 - [AK4586 MSB stuffing 2001/12 ...
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... MS0097-E-01 Table 20. Fields of burst info [AK4586] Repetition time of burst in IEC60958 frames 4096 1536 384 1152 1152 384 1152 512 1024 ...
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... MS0097-E- Repetition time >4096 frames Figure 32. Timing example 1 <20mS (Lock time) Stop 2~3 Syncs (B Figure 33. Timing example [AK4586 INT0 hold time <Repetition time Pc ...
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... AVSS, DVSS and PVSS must be connected the same analog ground plane. - Digital signals, especially clocks, should be kept away from the R pin in order to avoid an effect to the clock jitter performance case of coaxial input, ground of RCA connector and terminator should be connected to PVSS of the AK4586 with low impedance on PC board. MS0097-E-01 ...
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... VREFH Vpp (typ). The ADC output data format 2’s compliment. The DC offset is removed by the internal HPF. The AK4586 samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of 64fs. The AK4586 includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs. ...
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... ASAHI KASEI 44pin LQFP (Unit: mm) 12.80 0.30 10. 0.37 0.10 0.15 Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: MS0097-E-01 PACKAGE 1.70max 0.60 0.20 Epoxy Cu Solder plate - 53 - [AK4586] 0 0.2 0.17 0.05 2001/12 ...
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... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0097-E-01 MARKING AK4586VQ XXXXXXX 1 1) Pin #1 indication 2) Date Code: XXXXXXX(7 digits) 3) Marking Code: AK4586VQ 4) Asahi Kasei Logo IMPORTANT NOTICE - 54 - [AK4586] 2001/12 ...