ak4647vq AKM Semiconductor, Inc., ak4647vq Datasheet - Page 20

• Manufacturer Part Number: ak4647vq
• Description: Stereo Codec With Mic/hp-amp
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
„ PLL Unlock State
1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
In this mode, LRCK and BICK pins go to “L” and irregular frequency clock is output from MCKO pins at MCKO bit is
“1” before the PLL goes to lock state after PMPLL bit = “0” Æ “1”. If MCKO bit is “0”, MCKO pin goes to “L” (see
Table 7).
After the PLL is locked, a first period of LRCK and BICK may be invalid clock, but these clocks return to normal state
after a period of 1/fs.
When sampling frequency is changed, BICK and LRCK pins do not output irregular frequency clocks but go to “L” by
setting PMPLL bit to “0”.
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
In this mode, an invalid clock is output from MCKO pin before the PLL goes to lock state after PMPLL bit = “0” Æ “1”.
After that, the clock selected by Table 9 is output from MCKO pin when PLL is locked. ADC and DAC output invalid
data when the PLL is unlocked. For DAC, the output signal should be muted by writing “0” to DACL, DACH and DACS
bits.
MS0566-E-00
PLL State
After that PMPLL bit “0” Æ “1”
PLL Unlock (except above case)
PLL Lock
Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
PLL State
After that PMPLL bit “0” Æ “1”
PLL Unlock
PLL Lock
MCKO bit = “0”
“L” Output
“L” Output
“L” Output
MCKO pin
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MCKO bit = “0”
MCKO bit = “1”
“L” Output
“L” Output
“L” Output
See Table 9
Invalid
Invalid
MCKO pin
MCKO bit = “1”
See Table 10
“L” Output
Invalid
Invalid
Output
BICK pin
Invalid
“L” Output
LRCK pin
1fs Output
Invalid
[AK4647]
2006/11