ak4645 ETC-unknow, ak4645 Datasheet - Page 26

• Manufacturer Part Number: ak4645
• Description: Stereo Codec With Mic/hp-amp
• Manufacturer: ETC-unknow

ASAHI KASEI
When PLL reference clock input is LRCK or BICK pin, the sampling frequency is selected by FS3 and FS1-0 bits. (See
Table 7). FS2 bit is “don’t care”.
1) PLL Master Mode (AIN3 bit = “0”; PMPLL bit = “1”, M/S bit = “1”)
In this mode, LRCK and BICK pins go to “L” and irregular frequency clock is output from MCKO pins at MCKO bit is
“1” before the PLL goes to lock state after PMPLL bit = “0”
Table 8).
After the PLL is locked, a first period of LRCK and BICK may be invalid clock, but these clocks return to normal state
after a period of 1/fs.
When sampling frequency is changed, BICK and LRCK pins do not output irregular frequency clocks but go to “L” by
setting PMPLL bit to “0”.
2) PLL Slave Mode (AIN3 bit = “0”, PMPLL bit = “1”, M/S bit = “0”)
In this mode, an invalid clock is output from MCKO pin before the PLL goes to lock state after PMPLL bit = “0”
After that, the clock selected by Table 10 is output from MCKO pin when PLL is locked. ADC and DAC output invalid
data when the PLL is unlocked. For DAC, the output signal should be muted by writing “0” to DACL and DACH bits.
MS0543-E-00
PLL State
After that PMPLL bit “0”
PLL Unlock (except above case)
PLL Lock
PLL Unlock State
Others
Mode
0
1
2
3
6
7
Table 7. Setting of Sampling Frequency at PMPLL bit = “1” (Reference Clock = LRCK or BICK pin)
Table 8. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
Table 9. Clock Operation at PLL Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
PLL State
After that PMPLL bit “0”
PLL Unlock
PLL Lock
FS3 bit
0
0
0
0
1
1
“1”
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
FS2 bit
MCKO bit = “0”
Others
“L” Output
“L” Output
“L” Output
FS1 bit
0
0
1
1
1
1
“1”
MCKO pin
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MCKO bit = “0”
FS0 bit
MCKO bit = “1”
“L” Output
“L” Output
“L” Output
0
1
0
1
0
1
See Table 10
“1”. If MCKO bit is “0”, MCKO pin goes to “L” (see
Invalid
Invalid
Sampling Frequency Range
MCKO pin
12kHz < fs ≤ 16kHz
16kHz < fs ≤ 24kHz
24kHz < fs ≤ 32kHz
32kHz < fs ≤ 48kHz
8kHz < fs ≤ 12kHz
7.35kHz ≤ fs ≤ 8kHz
MCKO bit = “1”
N/A
See Table 11
“L” Output
Invalid
Invalid
Output
BICK pin
Invalid
Default
“L” Output
LRCK pin
1fs Output
Invalid
[AK4645]
2006/09
“1”.