ak4645 ETC-unknow, ak4645 Datasheet - Page 56

• Manufacturer Part Number: ak4645
• Description: Stereo Codec With Mic/hp-amp
• Manufacturer: ETC-unknow

ASAHI KASEI
When DACL bit is “1”, Lch/Rch signal of DAC is output from the LOUT/ROUT pins which is single-ended. When
DACL bit is “0”, output signal is muted and LOUT/ROUT pins output VCOM voltage. The load impedance is 10kΩ
(min.). When the PMLO=LOPS bits = “0”, the stereo line output enters power-down mode and the output is pulled-down
to AVSS by 2Ω(typ). When the LOPS bit is “1”, stereo line output enters power-save mode. Pop noise at power-up/down
can be reduced by changing PMLO bit at LOPS bit = “1”. In this case, output signal line should be pulled-down to AVSS
by 20kΩ after AC coupled as Figure 46. Rise/Fall time is 300ms(max) at C=1µF and AVDD=3.3V. When PMLO=LOPS
bits = “1”, stereo line output is in normal operation.
LOVL bit set the gain of stereo line output.
When LOM bit = “1”, DAC output signal is output to LOUT and ROUT pins as (L+R)/2 mono signal.
When LOM3 bit = “1”, the signal selected by MICL3 and MICR3 bits (LIN3/RIN3 inputs or MIC-Amp outputs) to
LOUT and ROUT pins as (L+R)/2 mono signal.
MS0543-E-00
Stereo Line Output (LOUT/ROUT pins)
Figure 46. External Circuit for Stereo Line Output (in case of using Pop Reduction Circuit)
LOPS
0
1
Table 50. Stereo Line Output Mode Select (x: Don’t care)
LOVL
PMLO
0
1
0
1
0
1
DAC
Table 51. Stereo Line Output Volume Setting
Figure 45. Stereo Line Output
+2dB
Gain
0dB
Normal Operation
“DACL”
Power-down
Power-save
Power-save
ROUT
LOUT
Mode
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Output Voltage (typ)
0.757 x AVDD
0.6 x AVDD
1µF
“LOVL”
220Ω
Pull-down to AVSS
Fall down to AVSS
Normal Operation
Rise up to VCOM
LOUT/ROUT pin
Default
20kΩ
ROUT pin
LOUT pin
Default
[AK4645]
2006/09