ak4628 AKM Semiconductor, Inc., ak4628 Datasheet
ak4628
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ak4628 Summary of contents
Page 1
... ADC for passing audio data to the primary audio output port. Control may be set directly by pins or programmed through a separate serial interface. The AK4628 has a dynamic range of 102dB for ADC, 106dB for DAC and is well suited for digital surround for home theater and car audio. An AC-3 system can be built with a IEC60958(SPDIF) receiver such as the AK4112B ...
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... HPF HPF DATT MCLK LRCK BICK DATT DATT Format Converter DATT SDOUT DATT SDIN1 DATT SDIN2 SDIN3 SDIN4 DATT DATT - 2 - [AK4628] RX1 RX2 RX3 RX4 XTI XTO DIR MCLK MCKO LRCK AK4112B LRCK BICK BICK DAUX SDTO LRCK AC3 SDOS BICK ...
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... AK4628VQ AKD4628 T Pin Layout SDOS 1 I2C 2 SMUTE 3 BICK 4 LRCK 5 SDTI1 6 SDTI2 7 SDTI3 8 SDTO 9 DAUX 10 DFS0 11 MS0211-E-02 -40 +85 C 44pin LQFP(0.8mm pitch) Evaluation Board for AK4628 AK4628VQ Top View - 3 - [AK4628] 33 DZF2/OVF 32 RIN 31 LIN TST2 28 ROUT1 27 LOUT1 26 ROUT2 25 LOUT2 24 ROUT3 23 LOUT3 2004/03 ...
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... Not available 01H Not available 09H Not available MS0211-E-02 AK4628 Up to 192kHz Available 128 levels Soft mute function is not independent of Digital attenuator. Available AK4628 DFS0 TST1 TST2 TDM0 AK4628 TDM0 TDM1 DFS0 DFS1 CKS1, CKS0 PD4, PD3, PD2, PD1 - 4 - [AK4628] 2004/03 ...
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... Digital Ground Pin PDN I Power-Down & Reset Pin When “L”, the AK4628 is powered-down and the control registers are reset to default state. If the state of P/S or CAD1-0 changes, then the AK4628 must be reset by PDN. 18 TST1 I Test Pin This pin should be connected to DVSS. ...
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... The group 1 and 2 can be selected by DZFM3-0 bits if P/S = “L” and DZFE = “L”. 3. This pin becomes OVF pin if OVFE bit is set to “1” at serial control mode. 4. All digital input pins except for pull-down should not be left floating. MS0211-E-02 Function (Note 2) (Note bus control mode 2 C Bus Bus [AK4628] 2004/03 ...
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... Notes: 5. All voltages with respect to ground. 7. The power up sequence between AVDD, DVDD and TVDD is not critical. Do not turn off only the AK4628 under the condition that a surrounding device is powered on and the I2C bus is in use. WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet. ...
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... PSR is applied to AVDD, DVDD and TVDD with 1kHz, 50mVpp. VREFH pin is held a constant voltage. 11. S/N measured by CCIR-ARM is 102dB(@fs=48kHz). MS0211-E-02 ANALOG CHARACTERISTICS min 2.90 (Note 9) 15 (Note 10 2.75 5 (Note 10 [AK4628] typ max Units 24 Bits 102 102 dB 102 102 dB 110 dB 0.2 0 ppm/ C 3.10 3.30 Vpp ...
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... Notes: 12. TVDD= (typ). 0.1mA 13. In the power-down mode. All digital input pins including clock pins (MCLK, BICK, LRCK) are held DVSS. MS0211-E-02 min typ 45 34 (Note 12 (Note 13 [AK4628] max Units 200 µA 2004/03 ...
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... FR (Note 16) DC CHARACTERISTICS Symbol min VIH 2.2 VIL - Iout=-100µA) VOH TVDD-0.5 Iout=-100µA) VOH AVDD-0.5 VOL - Iout= 100µA) Iout= 3mA) VOL - (Note 17) Iin - - 10 - [AK4628] typ max Units 18.9 kHz 20.0 - kHz 23.0 - kHz kHz dB 0. 1/fs 0 µs 1.0 Hz 6.5 Hz 21.8 kHz 24 ...
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... Units 12.288 MHz ns ns 18.432 MHz ns ns 24.576 MHz kHz 96 kHz 192 kHz kHz kHz ns ns ...
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... PDN Pulse Width PDN “ ” to SDTO valid Notes: 19. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. 20. The AK4628 can be reset by bringing PDN “L” to “H” upon power-up. 21. These cycles are the number of LRCK rising from PDN rising ...
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... MS0211-E-02 1/fCLK tCLKH tCLKL 1/fsn, 1/fsd tBCK tBCKH tBCKL Clock Timing (TDM= “0”) 1/fCLK tCLKH tCLKL 1/fs tLRH tLRL tBCK tBCKH tBCKL Clock Timing (TDM= “1” [AK4628] VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL 2004/03 ...
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... SDTI LRCK tBLR BICK SDTO SDTI MS0211-E-02 tLRB tSDS tSDH Audio Interface Timing (TDM= “0”) tLRB tSDS tSDH Audio Interface Timing (TDM= “1” [AK4628] VIH VIL VIH VIL tBSD 50%TVDD VIH VIL VIH VIL VIH VIL tBSD 50%TVDD VIH ...
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... MS0211-E-02 tCCKL tCCKH tCDS tCDH tHIGH tF tSU:DAT tSU:STA Start Bus mode Timing tPDV Power-down & Reset Timing - 15 - [AK4628] VIH VIL VIH VIL VIH A4 VIL tCSW VIH VIL tCSH VIH VIL VIH VIL VIH VIL tSP VIH VIL tSU:STO ...
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... If the external clocks are not present, the AK4628 should be in the power-down mode (PDN = “L” the reset mode (RSTN = “0”). After exiting reset at power-up etc., the AK4628 is in the power-down mode until MCLK and LRCK are input. ...
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... Table 6. System Clock Example (Auto Setting Mode) T De-emphasis Filter The AK4628 includes the digital de-emphasis filter (tc=50/15µs) by IIR filter. De-emphasis filter is not available in Double Speed Mode and Quad Speed Mode. This filter corresponds to three sampling frequencies (32kHz, 44.1kHz, 48kHz). De-emphasis of each DAC can be set individually by register data of DEMA1-C0 (DAC1: DEMA1-0, DAC2: DEMB1-0, DAC3: DEMC1-0, DAC4: DEMD1-0, see “ ...
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... SDTO SDTI1, SDTI2 24bit, Left 20bit, Right 0 justified justified 24bit, Left 24bit, Right 1 justified justified 24bit, Left 24bit, Left 0 justified justified 24bit 24bit [AK4628] LRCK BICK I/O I/O I 48fs 48fs Default I I 48fs I I 48fs LRCK BICK I/O I/O I 256fs I I 256fs ...
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... Lch Data Figure 4. Mode 3 Timing - 19 - [AK4628 ...
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... L3 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK Figure 8. Mode 7 Timing - 20 - [AK4628 ...
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... BICK 32 BICK Figure 11. Mode 10 Timing - 21 - [AK4628 ...
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... BICK 32 BICK Figure 12. Mode 11 Timing - 22 - [AK4628 ...
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... ASAHI KASEI T Overflow Detection The AK4628 has overflow detect function for analog input. Overflow detect function is enable if OVFE bit is set to “1” at serial control mode. OVF pin goes to “H” if analog input of Lch or Rch overflows (more than -0.3dBFS). OVF output for overflowed analog input has the same group delay as ADC (GD = 16/fs = 333 s @fs=48kHz). OVF is “ ...
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... ASAHI KASEI T Digital Attenuator AK4628 has channel-independent digital attenuator (128 levels, 0.5dB step). Attenuation level of each channel can be set by each ATT7-0 bits (Table 13). Table 13. Attenuation level of digital attenuator Transition time between set values of ATT7-0 bits can be selected by ATS1-0 bits (Table 14). Transition between set values is the soft transition ...
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... DZF “H”. T System Reset The AK4628 should be reset once by bringing PDN = “L” upon power-up. The AK4628 is powered up and the internal timing starts clocking by LRCK “ ” after exiting reset and power down state by MCLK. The AK4628 is in the power-down mode until MCLK and LRCK are input ...
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... ASAHI KASEI T Power-Down The ADC and DACs of AK4628 are placed in the power-down mode by bringing PDN “L” and both digital filters are reset at the same time. PDN “L” also reset the control registers to their default values. In the power-down mode, the analog outputs go to VCOM voltage and DZF1-2 pins go to “ ...
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... There is a delay, 4~5/fs from RSTN bit “0” to the internal RSTN bit “0”. MS0211-E-02 4~5/fs (9) 1~2/fs (9) (1) 516/fs Digital Block Power-down Init Cycle Digital Block Power-down Normal Operation (2) GD (3) “0”data “0”data (2) GD (6) (5) (6) (7) Don’t care 4 5/fs (8) Figure 15. Reset sequence example - 27 - [AK4628] Normal Operation GD (4) GD 2004/03 ...
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... ASAHI KASEI T DAC partial Power-Down Function All DACs of AK4628 can be powered-down individually by PD1-4 bits. The analog part of DAC is in power-down by PD1-4 bits =”1”, however, the digital part is not in power-down by it. Even if all DACs were set in power-down by the partial power-down bits, the digital part continue to function. The analog output of the channel which is set in power-down by PD1-4 bits is fixed to the voltage of VCOM ...
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... ASAHI KASEI T Serial Control Interface The AK4628 can control its functions via registers. Internal registers may be written by 2 types of control mode. The chip address is determined by the state of the CAD0 and CAD1 inputs. PDN = “L” initializes the registers to their default values. Writing “0” to the RSTN bit can initialize the internal timing circuit. But in this case, the register data is not be initialized. When the state of P/S pin is changed, the AK4628 should be reset by PDN pin. * Writing to control register is invalid when PDN = “ ...
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... SCL is HIGH defines a STOP condition (Figure 22). The AK4628 is capable of more than one byte write operation by one sequence. After receipt of the third byte, the AK4628 generates an acknowledge, and awaits the next data again. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred ...
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... MASTER S START CONDITION SDA SCL MS0211-E-02 Figure 22. START and STOP conditions Figure 23. Acknowledge on the I C-bus data line change stable; of data data valid allowed 2 Figure 24. Bit transfer on the I C-bus - 31 - [AK4628] P stop condition not acknowledge acknowledge 8 9 clock pulse for acknowledgement 2004/03 ...
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... ATT4 ATT6 ATT5 ATT4 ATT6 ATT5 ATT4 DEMA1 DEMA0 0 PD4 ATS1 ATS0 DZFM3 DZFM2 DZFM1 ATT6 ATT5 ATT4 ATT6 ATT5 ATT4 - 32 - [AK4628 DIF1 DIF0 0 SMUTE SDOS DFS0 ACKS ATT3 ATT2 ATT1 ATT0 ATT3 ATT2 ATT1 ATT0 ATT3 ATT2 ATT1 ATT0 ...
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... Register bit of TDM0 is ORed with the TDM0 pin if P/S = “L”. TDM0 pin should be “L” if the register control is used. MS0211-E- TDM1 TDM0 SDTI Sampling Speed 0 1-4 Normal, Double, Four Times Speed 1 1 Normal Speed 1 1-2 Normal, Double Speed - 33 - [AK4628 DIF1 DIF0 0 SMUTE 2004/03 ...
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... In the case of PWADN=”0” and PWDAN=”0”, the setting of LOOP1-0 becomes invalid. And ADC is selected. And it becomes the n MS0211-E- DFS1 LOOP1 LOOP0 ormal operation (No loop back [AK4628 SDOS DFS0 ACKS 2004/03 ...
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... ATT7 ATT6 ATT5 ATT4 ATT7 ATT6 ATT5 ATT4 DEMD1 DEMD0 DEMA1 DEMA0 [AK4628 ATT3 ATT2 ATT1 ATT0 ATT3 ATT2 ATT1 ATT0 ATT3 ATT2 ATT1 ATT0 ATT3 ATT2 ATT1 ATT0 ATT3 ATT2 ATT1 ATT0 ...
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... Disable, pin#33 becomes DZF2 pin. 1: Enable, pin#33 becomes OVF pin. MS0211-E- PD4 ATS1 ATS0 DZFM3 DZFM2 DZFM1 DZFM0 [AK4628 PD3 PD2 PD1 RSTN PWVRN PWADN PWDAN 2004/03 ...
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... LOUT1 ROUT2 LOUT2 ROUT3 LOUT3 0.1u 10u + Figure 25. Typical Connection Diagram - 37 - [AK4628 MUTE 27 MUTE 26 MUTE 25 MUTE 24 MUTE 23 MUTE MUTE MUTE ...
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... VREFH Vpp (typ)@fs=48kHz. The ADC output data format 2’s compliment. The DC offset is removed by the internal HPF. The AK4628 samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of 64fs. The AK4628 includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs. ...
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... DC offsets on analog outputs are eliminated by AC coupling since DAC outputs have DC offsets of a few mV. T Peripheral I/F Example The AK4628 can accept the signal of device with a nominal 3.3V supply because of TTL input. The power supply for output buffer (TVDD) of the AK4628 should be 3.3V when the peripheral devices operate at a nominal 3.3V supply. ...
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... ASAHI KASEI 44pin LQFP (Unit: mm) 12.80 0.30 10. 0.37 0.10 0.15 T Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: MS0211-E-02 PACKAGE 1.70max 0.60 0.20 Epoxy Cu Solder (Pb free) plate - 40 - [AK4628] 0 0.2 0.17 0.05 2004/03 ...
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... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0211-E-02 MARKING AK4628VQ XXXXXXX 1 1) Pin #1 indication 2) Date Code: XXXXXXX(7 digits) 3) Marking Code: AK4628VQ 4) Asahi Kasei Logo IMPORTANT NOTICE - 41 - [AK4628] 2004/03 ...