ak4683 AKM Semiconductor, Inc., ak4683 Datasheet - Page 42

• Manufacturer Part Number: ak4683
• Description: Asynchronous Multi-channel Audio Codec With Dir/t
• Manufacturer: AKM Semiconductor, Inc.

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The each block of the AK4683 are placed in the power-down mode by bringing PDN pin “L” and both digital filters are
reset at the same time. PDN pin “L” also reset the control registers to their default values. In the power-down mode, the
analog outputs go to VCOM voltage and SDTOA,B, DZF/OVF pin go to “L”. This reset should always be done after
power-up.
In slave mode, after exiting reset at power-up etc., the AK4683 starts to operate from the rising edge of LRCK after
MLCK, then the device is in the power-down mode until MCLK and LRCK are input. In slave mode or Internal Loop
Mode, the AK4683 starts to operate by the input of MLCK after exiting reset.
The analog initialization cycle of ADC starts after exiting the power-down mode. Therefore, the output data, SDTO
becomes available after 522/fs cycles of LRCK clock. In case of the DAC, an analog initialization cycle starts after
exiting the power-down mode. The analog outputs are VCOM voltage during the initialization. Figure 23 hows the
sequences of the power-down and the power-up.
The ADC and all DACs can be powered-down individually by PWAD bit , PWDA bit and PWDA2-1 bits. These bits
don’t initialize the internal register values. When PWAD bit = “0” and selecting ADC, the SDTOA(SDTOB) pin goes
to “L”. When PWDA bit and PWDA1-2 bits = “0”, the analog outputs go to VCOM voltage and DZF/OVF pin go to
“H”. Since some click noise may occur, the analog output should muted externally if the click noise influences system
application.
Notes:
MS0427-E-02
Power ON/OFF Sequence
(1) The analog part of ADC is initialized after exiting the power-down state.
(2) The analog part of DAC is initialized after exiting the power-down state.
(3) Digital output corresponding to analog input and analog output corresponding to digital input have the group
(4) ADC output is “0” data at the power-down state.
(5) Click noise occurs at the end of initialization of the analog part. Please mute the digital output externally if the
(6) Click noise occurs at the falling edge of PDN and at 512/fs(DAC1) and 512/fs +96ms(DAC2) after the rising
(7) When the external clocks
(8) DZF/OVF pin is “L” in the power-down mode (PDN pin = “L”).
(9) Please mute the analog output externally if the click noise (6) influences system application.
(10) DZF pin = “L” for 10∼11/fs after PDN= “↑”.
edge of PDN.
power-down mode.
delay (GD).
click noise influences system application.
Clock In
MCLK,LRCK,SCLK
DZF1/DZF2
DAC Internal
DAC In
DAC Out
ADC Internal
ADC In
ADC Out
External
PDN
Power
(Digital)
(Analog)
(Analog)
(Digital)
Mute
State
State
Don’t care
“0”data
“0”data
(MCLK, BICKA (BICKB), LRCKA (LRCKB))
(9)
(4)
Figure 23. Power-down/up sequence example
10∼11/fs (10)
Init Cycle
516/fs
Init Cycle
522/fs
Mute ON
(2)
(1)
(6)
(5)
- 42 -
GD
Normal Operation
Normal Operation
GD
(3)
(3)
are stopped, the AK4683 should be in the
GD
GD
Mute ON
Power-down
Power-down
(6)
(8)
(7)
Don’t care
“0”data
“0”data
[AK4683]
2007/04