ak4117 AKM Semiconductor, Inc., ak4117 Datasheet - Page 21

• Manufacturer Part Number: ak4117
• Description: Low Power 192khz Digital Audio Receiver
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
The DIF2-0 bits can select six serial data formats as shown in Table 9. In all formats, the serial data is MSB-first, 2’s
compliment format. The SDTO is clocked out on the falling edge of BICK and the DAUX is latched on the rising edge of
BICK. BICK outputs 64fs clock. When the SDTO format is equal or less than 20 bits (Mode 0-2), LSBs in the sub-frame
are truncated. In Modes 3-7, the last four LSBs are auxiliary data (see Figure 20).
When a Parity Error, Biphase Error or Frame Length Error occurs in a sub-frame, the AK4117 continues to output the
last normal sub-frame data from SDTO repeatedly until the error is removed. When an Unlock Error occurs, the AK4117
outputs “0” from SDTO. When using the DAUX pin, the data is transformed and output from SDTO. The DAUX pin is
used in Clock Operation Modes 1, 3 and in the unlock state of Mode 2. The input data format to DAUX should be
left-justified except in Mode 5. In Mode 5, both the input data format of DAUX and the output data format of SDTO are
I
MS0157-E-03
2
S.
Audio Serial Interface Format
Mode
0
1
2
3
4
5
6
7
DIF2 DIF1 DIF0
0
0
0
0
1
1
1
1
0
preamble
0
0
1
1
0
0
1
1
3 4
MSB
23
LSB
0
1
0
1
0
1
0
1
Aux.
7 8
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, I
AK4117 Audio Data (MSB First)
Figure 20. Bit configuration
Table 9. Audio data format
DAUX
2
11 12
S
sub-frame of IEC60958
- 21 -
16bit, Right justified
18bit, Right justified
20bit, Right justified
24bit, Right justified
24bit, Left justified
24bit, I
Reserved
2
SDTO
S
MSB
LSB
27 28 29 30 31
0
V U C P
LRCK
H/L
H/L
H/L
H/L
H/L
L/H
Default
[AK4117]
2004/04