ak4182a AKM Semiconductor, Inc., ak4182a Datasheet - Page 12

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ak4182a

Manufacturer Part Number
ak4182a
Description
Touch Screen Controller
Manufacturer
AKM Semiconductor, Inc.
Datasheet

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ASAHI KASEI
It is recommended that the control command is sent to fix the internal register value to be 00H when first power up. This initiates
all registers such as A2-0 bit, MODE bit, SER/DFR bit, PD1 bit and PD0 bit. The sequence is that 1) Power On with CSN = “L” or
“H” then CSN = “H”. 2) Send control command after CSN = “L”. 3) CSN = “H” again. Once sending command to fix the internal
register after first power up, the state of AK4182A is held on the known-condition of state as last command issued.
The AK4182A supports sleep mode that enables touch panel to put open state and disables pen interrupt function. The AK4182A
goes into sleep mode when the AK4182A gets the sleep control command. The selection of the Sleep mode is set by “MODE” bit.
The state of both the output of the PENIRQN pin and the connection with touch panel interface (XP, YP, XN, and YN) are the
following
The AK4182A keeps the sleep mode until it receives next control command.
The timing of going into the Sleep mode is the rising edge of the 8
AK4182A goes into normal operation out of sleep mode when the normal control command receives. The initial state after power
up is in a normal state.
Power-down is controlled by two bits, PD0 bit and PD1 bit. The power-down state of internal voltage reference is controlled by
PD1 bit, and is updated at the rising edge of 7
The power-down state of A/D converter, and touch screen driver switches is controlled by PD0 bit, and is updated at the rising
edge of 8
If PD0 bit is set to “1”, the state of the driver switches is maintained until the 5
MS0482-E-01
CSN is “H”, all driver switches except for YN switch switches are turned off and are open states. Only YN driver switch is turned
ON and YN pin is forced to the ground in this case.
PD1
0
0
1
1
Power on Sequence
Sleep mode
Power-down Control
111010XX
111000XX
command
th
PD0
Table
DCLK with CSN = “L”.
0
1
0
1
Control command
3. The AK4182A goes into the sleep mode with the power-down mode set by PD1, PD0 (refer to
PENIRQN
Disabled
Enabled
Enabled
Enabled
MODE
Auto Power-down Mode.
ADC ON Mode
VREF ON Mode
ADC and VREF ON Mode
A/D converter is automatically powered up at the start of the conversion, and goes to power- down
state automatically at the end of the conversion. And the AK4182A is always powered down at
this mode if CSN= “H”. All touch screen driver switches except for YN switch are turned off and
relative pins are open state. Only YN driver switch is turned ON and YN pin is forced to the
ground in this case. PEN interrupt function is enabled except for the tracking time and conversion
time even CSN= “L”. Please see “
reference is always power-down state.
A/D converter is always powered up while CSN = “L”. The internal voltage reference is always
power-down state. If X-axis or Y-axis is selected as analog input, touch screen driver switches are
always turned ON and the current flows through the touch plate if CSN= “L”. This is effective if
more settling time is required to suppress the electrical bouncing of touch plate.
The internal voltage reference is always powered up regardless of CSN state. ADC is auto power-
down mode. PEN interrupt function is enabled at all the period except for the period from the
5DCLK ↓ to 20DCLK ↓ regardless of CSN state.
A/D converter and the internal voltage reference is power-up state
PEN interrupt function is disabled and PENIRQN is forced to “H” state if CSN= “H”. The
behavior of PENIRQN is the same as “ADC ON Mode”
1
0
th
DCLK with CSN = “L”.
Normal Operation
Normal Operation
Table 3 Sleep Command Setting
Table 4 Power-down Control
PENIRQN
CSN=“L”
12
th
DCLK. This sleep mode is available when CSN = “H”.
Normal Operation
Normal Operation
PEN Interrupt
Touch Panel
Function
th
DCLK ↑ of the next conversion if CSN is “L”. If
” for the detail. The internal voltage
Output “H”
PENIRQN
Hi-z
CSN=“H”
Table
Touch Panel
[AK4182A]
Open
Open
2006/12
4).

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