ak4125 AKM Semiconductor, Inc., ak4125 Datasheet - Page 9

• Manufacturer Part Number: ak4125
• Description: 192khz / 24bit High Performance Asynchronous Src
• Manufacturer: AKM Semiconductor, Inc.

(Ta=25°C; AVDD, DVDD=3.0 ∼ 3.6V; C
Note 7. BICK rising edge must not occur at the same time as LRCK edge.
Note 8. The AK4125 can be reset by bringing the PDN pin = “L”.
MS0379-E-04
Parameter
Master Clock Timing
LRCK for Input data (ILRCK)
LRCK for Output data (OLRCK)
Audio Interface Timing
Reset Timing
PDN Pulse Width
Input PORT (Slave mode)
IBICK Period
IBICK Pulse Width Low
ILRCK Edge to IBICK “↑”
IBICK “↑” to ILRCK Edge
SDTI Hold Time from IBICK “↑”
SDTI Setup Time to IBICK “↑”
Input PORT (Master mode)
IBICK Frequency
IBICK Duty
IBICK “↓” to ILRCK
SDTI Hold Time from IBICK “↑”
SDTI Setup Time to IBICK “↑”
Output PORT (Slave mode)
OBICK Period
OBICK Pulse Width Low
OLRCK Edge to OBICK “↑”
OBICK “↑” to OLRCK Edge
OLRCK to SDTO (MSB) (Except I
OBICK “↓” to SDTO
Output PORT (Master mode)
OBICK Frequency
OBICK Duty
OBICK “↓” to OLRCK
OBICK “↓” to SDTO
Frequency
Pulse Width Low
Pulse Width High
Frequency
Duty Cycle
Frequency
Duty Cycle
Pulse Width High
Pulse Width High
(108kHz ∼ 216kHz)
(8kHz ∼ 108kHz)
(8kHz ∼ 108kHz)
(108kHz ∼ 216kHz)
Master Mode
Master Mode
Slave Mode
Slave Mode
SWITCHING CHARACTERISTICS
2
L
S mode)
(Note 7)
(Note 7)
(Note 7)
(Note 7)
(Note 8)
=20pF)
Symbol
tMBLR
tMBLR
tCLKH
tBCKH
tBCKH
tCLKL
tBCKL
tBCKL
dBCK
dBCK
fCLK
tBCK
tBCK
fBCK
tBCK
tBCK
fBCK
tLRB
tBLR
tSDH
tSDH
tLRB
tBLR
tBSD
tBSD
tSDS
tSDS
tLRS
Duty
Duty
Duty
Duty
tPD
fs
fs
- 9 -
0.4/fCLK
0.4/fCLK
1/128fs
1/128fs
1/64fs
1/64fs
1.024
min
−20
−20
−20
150
48
48
27
27
15
15
15
15
15
15
27
27
20
20
8
8
64fs
64fs
typ
50
50
50
50
50
50
41.472
max
216
216
52
52
20
20
20
20
20
[AK4125]
Units
MHz
2007/07
kHz
kHz
Hz
Hz
ns
ns
%
%
%
%
ns
ns
ns
ns
ns
ns
ns
ns
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
ns
ns
ns