ispgdx160a Lattice Semiconductor Corp., ispgdx160a Datasheet - Page 9

• Manufacturer Part Number: ispgdx160a
• Description: In-system Programmable Generic Digital Crosspoint
• Manufacturer: Lattice Semiconductor Corp.

1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to the Timing Model in this data sheet for further details.
PARAMETER #
Internal Timing Parameters
Inputs
t
GRP
t
MUX
t
t
Register
t
t
t
t
t
Data Path
t
t
t
t
t
t
t
Outputs
t
t
t
t
t
t
Clocks
t
t
Global Reset
t
io
grp
muxd
muxs
iolat
iosu
ioh
ioco
ior
rfdbk
iobp
ioob
muxc
muxc
iod
iod
ob
obs
oen
oedis
goe
toe
cio
gy0/1/2/3
gr
(Yx Clk)
(I/O Clk) 36 I/O Register I/O Input MUX Delay
(Yx Clk) 33 I/O Register Data Input MUX Delay
(I/O Clk) 34 I/O Register Data Input MUX Delay
21 Input Buffer Delay
22 GRP Delay
23 I/O Cell MUX A/B/C/D Data Delay
24 I/O Cell MUX A/B/C/D Data Select
25 I/O Latch Delay
26 I/O Register Setup Time Before Clock
27 I/O Register Hold Time After Clock
28 I/O Register Clock to Output Delay
29 I/O Reset to Output Delay
30 I/O Register Feedback Delay
31 I/O Register Bypass Delay
32 I/O Register Output Buffer Delay
35 I/O Register I/O Input MUX Delay
37 Output Buffer Delay
38 Output Buffer Delay, Slow Slew
39 I/O Cell OE to Output Enabled
40 I/O Cell OE to Output Disabled
41 Global Output Enable Delay
42 Test OE Enable Delay
43 I/O Clock Delay
44 Clock Delay, Y0/1/2/3
45 Global Reset to I/O Register/Latch
2
Over Recommended Operating Conditions
1
DESCRIPTION
1
9
Specifications ispGDX Family
MIN. MAX. MIN. MAX. UNITS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-5
12.3
0.7
2.0
1.0
2.5
1.6
1.6
2.4
1.6
0.7
0.2
0.4
0.1
1.1
2.1
4.1
5.1
0.9
5.9
0.8
0.8
2.5
8.2
0.7
2.4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-7
10.9
15.0
1.3
2.5
1.4
3.4
2.2
1.8
3.6
2.2
1.0
0.3
0.6
0.7
1.2
3.2
5.1
7.1
1.3
8.3
1.1
1.1
3.6
1.0
2.8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns