msm7719-01 Oki Semiconductor, msm7719-01 Datasheet - Page 5

• Manufacturer Part Number: msm7719-01
• Description: Echo Canceler With Adpcm Transcoder
• Manufacturer: Oki Semiconductor

MSM7719-01
¡ Semiconductor
MCKSL
Master clock selection input.
Set MCKSL to logic “0” when the master clock frequency is 9.6 to 10.0 MHz, and to logic “1”
when it is 19.2 to 20.0 MHz.
PCMACO
PCM data output of the echo canceler.
PCM is output from MSB in a sequential order, synchronizing with the rising edge of BCLKP and
SYNCP.
This pin is in a high impedance state except during 8-bit PCM output. When DTHR is set to logic
“1”, this pin becomes a 4-bit output and the input data to the input pin set by IOSL0-1 is output as
it is. In this case, this pin is in a high impedance state except during 4-bit output. Note that the echo
canceler signal output mode for this pin changes depending on the setting of IOSL0-1. (This pin is
also in a high impedance state during power-down or initial mode.)
Refer to Figs. 1-5.
PCMACI
PCM data input of the echo canceler.
PCM is shifted in at the falling edge of BCLKP and input from MSB.
The start of the PCM data (MSB) is identified at the rising edge of SYNCP. When DTHR is set to logic “1”,
this pin becomes a 4-bit input and the input data is output to the output pin set by IOSL0-1 as it is.
This pin is provided with a 500-kW pull-up resistor. Note that the echo canceler signal input mode
for this pin changes depending on the setting of IOSL0-1.
Refer to Figs. 1-5.
PCMADO
PCM data output.
PCM is serially output from MSB in synchronization with the rising edge of BCLKP and SYNCP.
This pin is in a high impedance state except during 8-bit PCM output. When DTHR is set to logic
“1”, this pin becomes a 4-bit output and the input data to the input pin set by IOSL0-1 is output as
it is. In this case, this pin is in a high impedance state except during 4-bit output.
Note that the signal ouput mode for this pin changes and the I/O control signal for this pin switches
between BCLKA/SYNCA and BCLKP/SYNCP depending on the setting of IOSL0-1. (This pin is
also in a high impedance state during power-down or initial mode.)
Refer to Figs. 1-5.
PCMADI
PCM data input.
PCM is shifted in at the falling edge of the BCLKP signal and input from MSB. The start of the PCM
data (MSB) is identified at the rising edge of SYNCP. When DTHR is set to logic “1”, this pin becomes
a 4-bit input and the input data is output to the output pin set by IOSL0-1 as it is. This pin is provided
with a 500-kW pull-up resistor. Note that the signal input mode for this pin changes and the I/O
control signal for this pin switches between BCLKA/SYNCA and BCLKP/SYNCP depending on
the setting of IOSL0-1.
Refer to Figs. 1-5.
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