msm7650 Oki Semiconductor, msm7650 Datasheet - Page 18

• Manufacturer Part Number: msm7650
• Description: Ntsc/pal Digital Encoder
• Manufacturer: Oki Semiconductor

¡ Semiconductor
CLOCK TIMING
Input Data Timing
Input data and sync signals are fed into the encoder at the rising edge of the clock.
Input data is handled as valid pixel data when t
Chrominance signal of input data at this time is regarded as Cb.
Input data is recognized as valid pixel data when input signal BLANK_L is high in the t
period.
When BLANK_L is high during the blanking period, however, input data is not output as valid
pixel data since processing to maintain blanking period is internally in-progress.
The values of t
follows.
In master mode
t
STA
Operation mode
CCIR 601 NTSC
Square Pixel NTSC
4Fsc NTSC
CCIR PAL
Square Pixel PAL
CLKX1
HSYNC_L
YD, CD
OLC, OLR
OLG, OLB
BLANK_L
–t
START
S1
=t
START
differ slightly in master mode and slave mode. The values of t
don't care
t
t
Video data input timing
START
STA
(Ts)
126
141
115
134
154
t
s1
ACTIVE VIDEO LINE
START
t
h1
VALID DATA
passes after the falling edge of HSYNC_L.
In slave mode
t
ACT
Operation mode
CCIR 601 NTSC
Square Pixel NTSC
4Fsc NTSC
CCIR PAL
Square Pixel PAL
don't care
t
STA
(Ts)
129
144
118
137
157
START
MSM7650
18/34
are as
ACT