msm7650 Oki Semiconductor, msm7650 Datasheet - Page 6

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msm7650

Manufacturer Part Number
msm7650
Description
Ntsc/pal Digital Encoder
Manufacturer
Oki Semiconductor
Datasheet
¡ Semiconductor
PIN DESCRIPTIONS (2/2)
55 to 57
65 to 72
73 to 80
Pin
46
47
48
49
50
51
52
53
54
58
59
60
61
62
63
64
I/O
I/O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
INTERLACE
to MODE[0]
YD0 to YD7
CD0 to CD7
RESET_L
MODE[2]
Symbol
TOUT1
TOUT2
TEST4
ADRS
GND
V
V
SDA
OLG
OLR
SCL
OLC
OLB
MS
DD3
DD5
Input pin 4 for testing. Normally, fixed to "0".
Output pin for testing
Output pin for testing
I
selected as subaddress.
1: 1000110/0: 1000100
I
I
System reset pin. "1" at an open state by an internal pull-up resistor
Operation mode select signal pin for synchronization circuit.
1: master/0: slave. "1" at an open state by an internal pull-up resistor
Interlace/noninterlace select signal pin.
1: interlaced/0: noninterlaced. "1" at an open state by an internal pull-up
resistor
Video mode select pins
These pins are valid when MR[7] is "1".
000: NTSC CCIR
100: PAL CCIR
"000" at an open state by an internal pull-down resistor
Transparent control signal
Overlay signal is displayed when this pin is "H".
Overlay text color (Blue component)
Overlay text color (Green component)
Overlay text color (Red component)
Digital GND
3.3V power supply
5.0V power supply
Digital image luminance signal data input pin
Level is based on ITU-601. YD7 is MSB.
Digital image chrominance signal data input pin
Level is based on ITU-601. CD7 is MSB.
2
2
2
C-bus subaddress setting pin. One of two addresses switchable can be
C-bus data pin
C-bus clock pin
001: NTSC Square Pixel
101: PAL Square Pixel
Description
010: NTSC 4Fsc
MSM7650
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