le79128 Zarlink Semiconductor, le79128 Datasheet - Page 23

• Manufacturer Part Number: le79128
• Description: Next Generation Voiceedge™ Control Processor Next Generation Carrier Chipset Ngcc
• Manufacturer: Zarlink Semiconductor

Note: CLKSTAT should only be written to cause a hardware reset. Any other write is illegal.
Table 11. CLKGEN Status Hardware Reset Controls
POR:
RST:
WDT
HWRES:
MCLK Configuration (MCLKCONFIG)
CURRENT_HIWAY:
REFCLK_FREQ:
Note: The power-up default for the 16-bit portion of this register is 0x12FB.
POR
x
0
0
0
0
1
D15
(R/W)
D7
(RW)
(R/W)
(R/W)
RSVD
RST
x
0
0
1
1
x
D14
(RO)
D6
(RW)
WDT
0
1
0
1
x
x
1: Clock failure detected
Power up reset indication. This bit is set by a POR event. It can be
cleared by writing 0 to it. This bit is cleared by firmware during the boot
sequence so that subsequent POR events can be detected. See
Table 11.
RST reset indication. This bit is cleared by a POR event and set by the
RST pin. It can be written by firmware. The RST bit is cleared by firmware
during the boot sequence so that subsequent RST events can be
detected. See Table 11.
WDT_OUT reset indication. This bit is cleared by a POR event and set by
the (!RST_N &&!WDT_OUT_N) asserted. The WDT bit is cleared by
firmware during the boot sequence so that subsequent WDT events can
be detected. See Table 11.
Hardware reset. Setting this bit causes a full system reset to occur
immediately. After the reset sequence, this bit will still hold the last written
value. See Table 11.
by hardware if either AUTO_HIWAY bit (in PCLKA_SEL, address 0x09) is
asserted and a clock failure is present on the appropriate PCLK/FS pair.
0: Highway A. (Default)
1: Redundant Highway.
Indicates the frequency of the selected PLL source clock. The field is read
only and the frequency should be programmed in the appropriate
PCLKx_SEL register (x =A or B). The frequency is specified as a:
(multiple of 8000) - 1.
Currently active PCM highway. This bit is writable but may be modified
CURRENT
_HIWAY
Microsemi Corporation - CMPG
RESET
D13
HW_
D5
0
1
1
1
1
1
Le79128
Host induced reset. Evaluate pin straps and perform full
Host induced reset. Start previously loaded application
23
Hardware induced reset. Follow pin strap options.
REFCLK_FREQ[7:0]
D12
D4
without MBIST or Code Loading.
Host induced reset. Reserved.
system startup sequence.
D11
D3
Reserved
Notes
REFCLK_FREQ[12:8]
Direct page address 0x0B (R/W)
D10
D2
Preliminary Data Sheet
D9
D1
D8
D0