le79128 Zarlink Semiconductor, le79128 Datasheet - Page 44

• Manufacturer Part Number: le79128
• Description: Next Generation Voiceedge™ Control Processor Next Generation Carrier Chipset Ngcc
• Manufacturer: Zarlink Semiconductor

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10. Assumes 150-pF load on MPCLK and a 50
25% of PCLK rising to rising*
75% of PCLK rising to rising*
Refer to Figure 26 for timing diagram test points.
The PCM clock (PCLK) frequency must be an integer multiple of 512 kHz +/- 6000 ppm and be specified to within 100ppm. The minimum
clock frequency is 512 kHz. The maximum clock frequency is limited by software to 8.192 MHz.
TSC is an open drain driver. t
dependent on the load circuitry. The minimum pull-up resistance to VDD is 360 Ω.
C
C
If PCLK is used to drive the main system clock, it must be present at all times to maintain proper internal operation. A total clock failure will
result in a 60% reduction in internal MIPs within 125 µs. If the clock failure can be restored within 2 µs, a MIP drop of only 1% will result. The
VCP device has the capability to detect an abrupt frequency change greater than 8% and switch within 2 us.
Maximum PCLK jitter is +/- 97ns or 1/2 of the PCLK period whichever is less.
The number of PCLKs per FS period may deviate by 1 clock (not by +/-1 which would be 2).
Data input setup and hold times occur within a sampling window which is referenced to an internal clock. Setup and hold times are specified
assuming standard firmware usage.
load
load
= 40 pF
= 150 pF
(Transmit on Negative PCLK Edge)
(Transmit on Negative PCLK Edge)
(Transmit on Negative PCLK Edge)
(Transmit on Positive PCLK Edge)
(Transmit on Positive PCLK Edge)
(Transmit on Positive PCLK Edge)
Sample point DX, DR, MDX, MDR
Sample point DX, DR, MDX, MDR
*Because the receive sampling point is defined from the rising edge, the clock duty cycle may affect
timing relative to the negative edge of the clock
DX, DR, MDX, MDR
DX, DR, MDX, MDR
(noted by up arrow)
(noted by up arrow)
TSO
is defined as the delay time the output driver turns off after the PCLK transaction. The actual delay time is
TSCXA/B
TSCXA/B
MPCLK
PCLK,
MFS
FS,
Ω
Figure 24. PCM Highway Timing
series termination at output of MPCLK.
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5
Microsemi Corporation - CMPG
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9
9
Le79128
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11
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11
First
Bit
6
First
4
Bit
12
12
10
8
Preliminary Data Sheet
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8
3
1
2