le79128 Zarlink Semiconductor, le79128 Datasheet - Page 42

• Manufacturer Part Number: le79128
• Description: Next Generation Voiceedge™ Control Processor Next Generation Carrier Chipset Ngcc
• Manufacturer: Zarlink Semiconductor

SPI1 and SPI2 Timing
Two Master SPI blocks are provided to communicate with the MPI interfaces of up to 8 OISLAC devices each. This interchip
highway carries control information between the VCP and the SLAC devices. Timing will be met as long as loading and signal
integrity issues are properly handled on the printed circuit board.
Note:
1.
2.
3.
Timing Requirements
Refer to Figure 26 for timing diagram test points.
Assumes 40-pF load on SPI_CLK, SPI_MOSI, and SPI2_CS or GPIO[31:16].
Assumes 150-pF load on SPI_CLK and SPI_MOSI, but 40-pF load on SPI2_CS or GPIO[31:16]. Assumes a 50
output of SPI_CLK.
Table 19. SPI1 and SPI2 Timing Parameters
No.
1
2
3
4
5
6
7
8
9
SPI2_CS/GPIO[31:16])
Symbol
t
t
t
t
MOSIH
MISOH
MOSIS
MISOS
t
t
t
t
t
t
t
DCY
DCH
DCR
CSO
DCL
DCF
CSS
SPI_CLK
MOSI
MISO
Data clock period
Data clock ON pulse width
Data clock OFF pulse width
Rise time of clock
Fall time of clock
Chip select setup to first clock edge
Chip select output delay
Data output setup to first clock edge
Data output hold time
MISO/MOSI(3-wire) input setup time
MISO/MOSI(3-wire) input hold time
8
4
6
Figure 23. SPI Timing Waveforms
Parameter
Microsemi Corporation - CMPG
1
Le79128
42
9
7
Min
114
34
77
—
—
—
—
62
62
50
50
15
2
1
1
0
Typ
129
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
1
3
Preliminary Data Sheet
3657.1
1809
1852
Max
—
—
15
—
—
15
15
—
—
5
8
5
8
Ω
series termination at
Unit
5
ns
Note
2
3
2
3
2
3
2
3
2
3