le79128 Zarlink Semiconductor, le79128 Datasheet - Page 24

• Manufacturer Part Number: le79128
• Description: Next Generation Voiceedge™ Control Processor Next Generation Carrier Chipset Ngcc
• Manufacturer: Zarlink Semiconductor

System Real Time Status (SYSSTAT)
This read only register allows the host to determine the present status of the system faults. It differs
from the INTPARAM register in that no interrupt is required to determine the system fault status.
EV_OV
WDT
CFAIL_GLOBAL
CFAIL_PCLKA
CFAIL_PCLKB
SYS_FLAG[9:0]
System Interrupt Mask (SYSMASK)
This register is used to mask system interrupt sources. There is a one to one correspondence
between the bit definitions in SYSMASK and INTIND when INTIND represents a system interrupt.
EVENT_DELAY: Event delay bit
MOVL:
EVENT_
DELAY
D15
D15
D7
D7
1
EV_OV
MOVL
D14
D14
D6
D6
Interrupt Queue Overflow mask. When asserted the interrupt is masked.
0: Low priority event queue (two, three) interrupts are reported to the host by
1: Low priority event queue (two, three) interrupts cannot pull the INT pin low or
output events unless a system interrupt or high priority event queue one inter-
rupt was first present to assert the INT pin. This feature allows fewer host inter-
ruption from the lower priority events.
asserting the INT pin whenever an event is present in those queues. (default)
PLL or selected source Clock Fail status. (default =1)
PCLKA/FSA Clock Fail status. (default =1)
PCLKB/FSB Clock Fail status. (default =1)
Software configurable system interrupt real time status bit.
Event queue overflow detected. This bit indicates that an event was lost
due to event queue overflow. If events are being serviced and generated
at the same time it is possible that this flag will be set multiple times. This
bit must be cleared by reading INTIND, if the bit is unmasked, or by
reading SYSSTAT if it is masked.
Watchdog timer timeout occurred. (default =0) This bit is asserted when
the WDT_OUT pin is driven low if a system reset is not induced by that
action.This bit must be cleared by reading INTIND, if the bit is unmasked,
or by reading SYSSTAT if it is masked.
0: The status of the bit is not set (default).
1: When asserted, each bit masks the interrupt caused by a transition on the
respective SYS_FLAG bit of the SYSSTAT register. The application software
will define the meaning of these bits as needed.
MWDT
Microsemi Corporation - CMPG
WDT
D13
D13
D5
D5
Le79128
MCFAIL_
GLOBAL
GLOBAL
24
CFAIL_
D12
D12
D4
D4
MSYS_FLAG[7:0]
SYS_FLAG[7:0]
MCFAIL_
CFAIL_
PCLKA
PCLKA
D11
D11
D3
D3
MCFAIL_
CFAIL_
PCLKB
PCLKB
Direct page address 0x0D (RW)
Direct page address 0x0C (RO)
D10
D10
D2
D2
Preliminary Data Sheet
D9
D1
D9
D1
MSYS_FLAG[9:8]
SYS_FLAG[9:8]
D8
D0
D8
D0