m21120 Mindspeed Technologies, m21120 Datasheet - Page 27
m21120
Manufacturer Part Number
m21120
Description
M21120 Crosspoint Switch Data Sheet
Manufacturer
Mindspeed Technologies
Datasheet
1.M21120.pdf
(38 pages)
- Current page: 27 of 38
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21120-DSH-001-B, 3/27/03
Table 16. Register Description (Continued)
2
1
0
6
5:4
3:2
1:0
en_refs
en_lp
muxdrv
coredrv[1:0]
ifdrv[1:0]
clkdrv[1:0]
Register e7h (xSET mode) needs to be set to 1 in order for this register to have any function.
Any value written to this register will update the ACL with the data from the ICL.
This bit must be set to 1.
0: all references down
1: references powered up (default)
Core SmartPower™ control.
0: core fully powered
1: core in low power mode (default)
MUX SELECT LINE slopes.
0: High drive (default)
1: Low drive.
READ BACK SPEED (Read back slope control)
00: high drive (default)
01: medium drive
10: low drive
11: tiny drive
WRITE SPEED (Write slope control)
00: high drive (default)
01: medium drive
10: low drive
11: tiny drive
CLOCK distribution slope
00: high drive (default)
01: medium drive
10: low drive
11: tiny drive
34 x 34 3.2 Gbps Crosspoint Switch with Input Equalization
EDh: slope control internal
EBh: Mindspeed reserved
Mindspeed Technologies™
E8h: software xSET
ECh: core control
M21120
Page 27 of 38
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