mt9074ap1 Zarlink Semiconductor, mt9074ap1 Datasheet
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... RxDLCLK RxDL Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2002-2005, Zarlink Semiconductor Inc. All Rights Reserved. T1/E1/J1 Single Chip Transceiver MT9074AL MT9074AP MT9074APR MT9074AL1 MT9074AP1 MT9074APR1 • Hardware data link access • JTAG Boundary Scan Applications • ...
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... ITU-T Recommendations including G.703, G.704, G.706, G.732, G.775, G.796, G.823 for PCM30, and I.431 for ISDN primary rate. It also supports ETSI ETS 300 011, ETS 300 166 and ETS 300 233. MT9074 bits and channel 16 (E1 mode). The LIU a 2 Zarlink Semiconductor Inc. Data Sheet ...
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... VSS IC 92 INT/MOT VDD R/W/WR AC0 100 100 PIN MQFP (JEDEC MO-112) Figure 2 - Pin Connections Zarlink Semiconductor Inc. MT9074 60 TxAO 59 Trst 58 Tclk 57 Tms 56 Tdo 55 Tdi 54 GNDATX 53 TRING 52 TTIP 51 VDDATX 50 VDD VSS RxFP ...
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... HDLC Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 HDLC Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 HDLC Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Slip Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Slip Buffer in T1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Slip Buffer in E1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Framing Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Frame Alignment in T1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Frame Alignment in E1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Notes for Synchronization State Diagram (Figure 15 MT9074 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Consecutive Frame Alignment Patterns (CONFAP Receive Frame Alignment Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Receive Non Frame Alignment Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Receive Multiframe Alignment Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Interrupts on T1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Interrupts on E1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Digital Framer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 T1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 E1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 MT9074 Table of Contents 5 Zarlink Semiconductor Inc. Data Sheet ...
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... Per Channel Transmit Signaling (Pages 5 and 6) (E1 121 Per Time Slot Control Words(Pages 7 and 8) (E1 122 Per Channel Receive Signaling (Pages 9 and 0AH) (E1 123 HDLC Control and Status (Page B for HDLC0 and Page C for HDLC1 125 MT9074 Table of Contents 6 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 31 - Multiframe Timing Diagram (T1 mode or E1 mode 146 Figure 32 - ransmit Digital Data Timing Diagram (LIU Disabled 147 Figure 33 - Receive Digital Data Timing Diagram (LIU Disabled 147 Figure Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Figure 35 - PCM30 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Figure 36 - ST-BUS Stream Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 MT9074 List of Figures 7 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 42 - Custom Pulse Word Table 43 - Custom Pulse Word Table 44 - Master Status 1 (Page 3) (T1 Table 45 - Synchronization Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 46 - Alarm Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 47 - Timer Status Word Table 48 - Most Significant Phase Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 MT9074 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 91 - Interrupt Mask Word One (E1 Table 93 - Interrupt Mask Word Three (E1 100 Table 92 - Interrupt Mask Word Two (E1 100 Table 94 - LIU Control Word (E1 101 Table 95 - Master Control 2 (Page 02H) (E1 102 Table 96 - Configuration Control Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 MT9074 List of Tables 9 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 140 - HDLC Address Recognition Register 126 Table 141 - HDLC Address Recognition Register2 (Page B & C, Address 11H 126 Table 142 - TX FIFO Write Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Table 143 - RX FIFO Read Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Table 144 - HDLC Control register 127 MT9074 List of Tables 10 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 151 - ransmit Byte Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Table 152 - HDLC Test Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Table 153 - HDLC Test Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Table 154 - HDLC Control Register 134 Table 155 - HDLC Control Register 135 MT9074 List of Tables 11 Zarlink Semiconductor Inc. Data Sheet ...
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... IRQ Interrupt Request (Output). A low on this output pin indicates that an interrupt request is presented. IRQ is an open drain output that should be connected to V through a pull-up resistor. An active low CS signal is not required for this pin to function. MT9074 Description 12 Zarlink Semiconductor Inc. Data Sheet DD ...
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... C1.50 RxDLCLK Data Link Clock (Output). A gapped clock signal derived from the extracted clock from the line clock, available for an external device to clock in RxDL data ( 12 kHz) on the rising edge. MT9074 Description 13 Zarlink Semiconductor Inc. Data Sheet ...
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... TRING signal - must be transformer coupled (See Figure 5 GND Transmit Analog Ground (Input). Analog ground for the LIU transmitter. ATx 55 43 Tdi IEEE 1149.1 Test Data Input. If not used, this pin should be pulled high. MT9074 Description 14 Zarlink Semiconductor Inc. Data Sheet ...
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... The MT9074 in T1 mode operates as an advanced T1 framer with an on-chip Line Interface Unit (LIU) that meets or supports the recommendations including ITU I.431, AT&T PUB43801, TR-62411, ANSI T1.102, T.403 and T.408. MT9074 Description (Ground) for normal operation Zarlink Semiconductor Inc. Data Sheet ...
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... DSTo with framing operations disabled, consequently, the data passes through the slip buffer and drives DSTo with an arbitrary alignment mode the S bits can be accessed by the MT9074 in the following three ways: a • Programming a register; MT9074 16 Zarlink Semiconductor Inc. Data Sheet ...
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... RT (as shown in Figure 5) are for termination for transmit return loss. The values of RT may be optimized for T1 mode, E1 120 Ω lines Ω lines or set at a compromise value to serve multiple applications. Program the LIU Control Word (address 1FH page 1) to adjust the pulse amplitude accordingly. MT9074 17 Zarlink Semiconductor Inc. Data Sheet ...
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... Jitter Amplitude (log scale) 18UI 1.5UI 0.2UI 1.667 Hz Figure 4 - Input Jitter Tolerance as recommended by ETSI 300 011 (E1) MT9074 100Hz 10Hz 1.0kHz 10kHz 100kHz 4.9 Hz MT9074 Tolerance 20 Hz 2.4 kHz 18 kHz 100 kHz 18 Zarlink Semiconductor Inc. Data Sheet Jitter Frequency (log scale) Jitter Frequency (log scale) ...
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... Fuse 1:2 Tx Fuse Ω 2.4 T Fuse 1:1 Fuse Rx 19 Zarlink Semiconductor Inc. Data Sheet * Recommended Rectifier bridge diodes are MUR460 (due to low capacitance). ** Recommended Zero-Diode is 1N5339 (due to high capacitance) ...
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... RRING Figure 6 - Analog Line Interface (E1) MT9074 Functional Description Ω ) RT( Ω ) Transformer Ratio 120 0 120 0 120 15 120 / 120 12.1 Fuse 1:2 T Fuse Fuse 1:1 Fuse 20 Zarlink Semiconductor Inc. Data Sheet 1:2 1:1 1:2 1:2 1:2 1:1 1:2 1 Termination resis- T tor. Please check Table 2 for specific resistor values. Rx ...
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... Figure 7 - Pulse Template (T1.403) (T1) -78 -.39 -.27 -.27 -.12 .05 .05 .8 1.2 1.2 1.05 Table 3 - Maximum Curve for Figure 7 -97 0 -.23 -.23 -.15 0 .15 -. .95 Table 4 - Minimum Curve for Figure 7 21 Zarlink Semiconductor Inc. Data Sheet 0 175 220 499 752 --- 0 .27 .34 .77 1.16 --- 1.05 -.05 .05 .05 --- 97 149 149 298 395 603 .23 ...
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... The MT9074 requires a 20 Mhz clock. This may provided ppm oscillator as per Figure 9. MT9074 269 nS 244 nS 194 nS Nominal Pulse 219 nS 488 nS Figure 8 - Pulse Template (G.703)(E1 Vdd 20 MHz OSC1 OUT GND OSC2 ( ) open Figure 9 - Clock Oscillator Circuit 22 Zarlink Semiconductor Inc. Data Sheet .1µF ...
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... MHz 50 ppm Fundamental Parallel Ω MHz OSC1 MΩ 100 Ω OSC2 Note: the 1 µH inductor is optional Figure 10 - Crystal Oscillator Circuit 40 Frequency (Hz) Figure 62411 Jitter Attenuation Curve 23 Zarlink Semiconductor Inc. Data Sheet µH* -20 dB/decade 400 10K ...
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... Each time slot is 8 bits in length and is transmitted most significant bit first (numbered bit 1). This results in a single time slot data rate of 8 bits x 8000/sec kbits/sec. MT9074 BS/LS S/ PLL locked to C4b 0 1 PLL locked to E1. PLL free - running. 24 Zarlink Semiconductor Inc. Data Sheet Note ...
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... It may free - run with the internal multiframe counters; MT9074 Zarlink Semiconductor Inc. Data Sheet ...
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... Mb/s digital stream DSTi. Note that the overhead bits extracted from the receive signal are mul- tiplexed into outgoing DSTo channel 31 bit SLC - 96 mode the transmit frame counters synchronize to the framing pattern clocked in on the TXDL input. MT9074 26 Zarlink Semiconductor Inc. Data Sheet ...
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... FPS FDL CRC CB1 CB2 CB3 CB4 CB5 CB6 Table 8 - ESF Superframe Structure (T1) 27 Zarlink Semiconductor Inc. Data Sheet Signaling A B Signaling ...
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... Table 9 - SLC-96 Framing Structure(T1) 28 Zarlink Semiconductor Inc. Data Sheet Ft Fs Notes Spoiler Bits Maintenance Field Bits Alarm Field Bits Line Switch Field Bits ...
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... Bit position one of the NFAS can be either a CRC-4 multiframe alignment signal, an E-bit or an international usage bit. Refer to an approvals laboratory and national standards bodies for specific requirements. MT9074 0 1,2,3...15 16 17,18,19,... 31 0 1,2,3...15 16 17,18,19,... 31 29 Zarlink Semiconductor Inc. Data Sheet ...
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... 14/FAS 15/NFAS Table 11 - FAS and NFAS Structure 30 Zarlink Semiconductor Inc. Data Sheet ...
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... CRC MFAS and transmit E-bits are the same state as the TE control bit. When CRCSYN = 0, the CRC MFAS search is terminated and the transmit RAI goes low. Automatic CRC-interworking is de-activated. Transmit RAI is low continuously. Automatic CRC-interworking is de-activated. Transmit RAI is high continuously. 31 Zarlink Semiconductor Inc. Data Sheet ...
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... Per Time Slot Control 00001001 (09H) Per Channel Receive Signaling 00001010 (0AH) Per Channel Receive Signaling 00001011 (0BH) HDLC0 Control and Status 00001100 (0CH) HDLC1 Control and Status MT9074 Register Description Table 13 - Page Summary 32 Zarlink Semiconductor Inc. Data Sheet Processor ST-BUS Access Access R R R/W R/W ...
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... Place the device into metallic loopback (set bit 6 address 15H of page mode - 7 line build out will also have to be programmed). (3) Wait until frame synchronization is achieved. (4) Clear the Bipolar Violation counters. (5) Wait 100 milliseconds. (6) Check for bipolar violation errors. If any occur reset the device and return to step (1). MT9074 33 Zarlink Semiconductor Inc. Data Sheet ...
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... Transmit FAS C 0011011 n Transmit non-FAS 1/S n 00001111 Data Link Deactivated CRC Interworking Activated Signaling CAS Registers Deactivated Interrupts Masked RxMF Output Signaling Multiframe Error Insertion Deactivated HDLCs Deactivated Counters Cleared Transmit Data All Ones Table 15 - Reset Status(E1) 34 Zarlink Semiconductor Inc. Data Sheet D4 1111111 ...
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... No DL data will be lost or repeated when a receive frame slip occurs. See the AC Electrical Characteristics for timing requirements. MT9074 bit position is clocked in from the TxDL pad (pin 65 in PLCC, pin Zarlink Semiconductor Inc. Data Sheet bits ( ...
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... CRC Error Event > 320 Severely - Errored Framing Event >=1 Frame Synchronization Bit Error Event >=1 Line code Violation Event >=1 Slip Event >=1 Payload Loopback Activated Under Study for sync. Reserved - set to 0 One Second Module 4 counter 36 Zarlink Semiconductor Inc. Data Sheet Content 01111110 EA 00111000 or 00111010 ...
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... In T1 mode, ESF Data Link (DL) can be connected to internal HDLC0, operating at a bit rate of 4 kbits/sec. HDLC0 can be activated by setting the control bit 5, address 12H in Master Control Page 0. Interrupts from HDLC0 are masked when it is disconnected. MT9074 37 Zarlink Semiconductor Inc. Data Sheet ...
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... FIFO minus the FCS which is discarded. MT9074 Data Field FCS Flag (7E) n Bytes Two One Byte ≥ Bytes 01111110 Table 17 - HDLC Frame Format +1” produces the 16-bit FCS. In the transmitter the FCS is 38 Zarlink Semiconductor Inc. Data Sheet ...
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... The Receiver and Transmitter can be enabled independent of one another through Control Register 1. The transceiver input and output are enabled when the enable control bits in Control Register 1 are set. Transmit to receive loopback as well as a receive to transmit loopback are also supported. Transmit and MT9074 39 Zarlink Semiconductor Inc. Data Sheet ...
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... Mark idle control bit. Tx FIFO underrun will occur if the FIFO empties and the last byte did not have either an EOP or FA tag. A frame abort sequence will be sent when an underrun occurs. MT9074 40 Zarlink Semiconductor Inc. Data Sheet ...
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... Byte status 1 1 last byte (bad packet first byte 1 0 last byte (good packet packet byte MT9074 41 Zarlink Semiconductor Inc. Data Sheet . If the data length between FCS When FIFO. code are loaded into the Rx FCS register should match CRC ...
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... Read Pointer Read Pointer Read Vectors Frame 0 Minimum Delay Write Vectors Frame 0 Read Vectors - Maximum Delay Figure 12 - Read and Write Pointers in the Transmit Slip Buffers MT9074 Frame 1 Frame 1 Frame 0 42 Zarlink Semiconductor Inc. Data Sheet Wander Tolerance Frame 1 ...
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... Network standards state that, within limits, trunk interfaces must be able to receive error-free data in the presence of jitter and wander (refer to network requirements for jitter and wander tolerance). The MT9074 will allow 92 usec (140 UI, DS1 unit intervals) of wander and low frequency jitter before a frame slip will occur. MT9074 43 Zarlink Semiconductor Inc. Data Sheet ...
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... Therefore single trunk system the receive data is in phase with the E1.5o clock, the C4b clock is phase-locked to the E1.5o clock, and the read and write positions of the slip buffer will remain fixed with respect to each other. MT9074 44 Zarlink Semiconductor Inc. Data Sheet ...
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... Conversely, if the read pointer MT9074 Read Pointer XXX Frame 1 XXX Frame 1 Frame 0 45 Zarlink Semiconductor Inc. Data Sheet Wander Tolerance XXX Frame 1 XXX ...
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... Until such time as a new frame alignment is achieved, the signaling bits are frozen in their states at the time that frame alignment was lost, and error counting for Ft, Fs, ESF framing pattern or CRC-6 bits is suspended. MT9074 Read Pointer -13 CH Read Pointer 46 Zarlink Semiconductor Inc. Data Sheet Wander Tolerance ...
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... When CRC-4 multiframing has been achieved, the primary basic frame alignment and resulting multiframe alignment will be adjusted to the basic frame alignment determined during CRC-4 synchronization. Therefore, the primary basic frame alignment will not be updated during the CRC-4 multiframing search, but will be updated when the CRC-4 multiframing search is complete. MT9074 47 Zarlink Semiconductor Inc. Data Sheet ...
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... RAI = 1 Notes 6 & 7. CRC-to-non-CRC interworking. Maintain primary basic frame alignment. Continue to send CRC-4 data, but stop CRC processing. E-bits set to ‘0’. Indicate CRC-to-non-CRC operation. Note 7. 48 Zarlink Semiconductor Inc. Data Sheet NO 3 consecutive incorrect frame alignment signals NO ...
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... A receive signaling bit debounce of 6 msec. can be selected (DBEn set high - Signaling Control Word, page 01H, address 14H). It should be noted that there may be as much as 3 msec. added to this duration because signaling equipment state changes are not synchronous with the D4 or ESF multiframe. MT9074 49 Zarlink Semiconductor Inc. Data Sheet ...
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... Digital loopback (DSTi to DSTo at the framer/LIU interface). Bit DLBK = 0 normal; DLBK = 1 activate. System b) Remote loopback (RTIP and RRING to TTIP and TRING respectively at the DS1 side). Bit RLBK = 0 normal; RLBK = 1 activate. System MT9074 MT9074 DSTi Tx DS1 DSTo MT9074 Tx DS1 DSTo Rx 50 Zarlink Semiconductor Inc. Data Sheet ...
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... DS1 link and to assist the designer in meeting specifications such as TR62411 and T1.403. All counters can be preset or cleared by writing to the appropriate locations. MT9074 MT9074 Tx DSTi DS1 DSTo MT9074 DSTi Tx DS1 DSTo Rx MT9074 DSTi Tx DS1 DSTo Rx MT9074 DSTi Tx DS1 DSTo Rx 51 Zarlink Semiconductor Inc. Data Sheet ...
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... Multiframes out of Sync Counter (MFOOF7-MFOOF0) This eight bit counter MFOOF7 - MFOOF0 is located on page 4 address 15H, and is incremented once per multiframe (1.5 ms for D4 and 3 ms for ESF) during the time that the framer is out of terminal frame synchronization. MT9074 52 Zarlink Semiconductor Inc. Data Sheet ...
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... There are two maskable interrupts associated with the E-bit error measurement. EBI (page 1, address 1CH) is initiated when the least significant bit of the counter toggles, and FEBEO (page 01H, address 1DH) is initiated when the counter overflows. MT9074 53 Zarlink Semiconductor Inc. Data Sheet ...
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... T1 mode or a total of 32 unique addresses in E1 mode. Each address controls a matching timeslot on the 24 DS1 channels (T1 PCM-30 channels (E1) and the equivalent channel data on the receive (DSTo) data. For example address 0 of the first per time slot control page contains program control for transmit timeslot 0 and DSTo channel 0. MT9074 54 Zarlink Semiconductor Inc. Data Sheet ...
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... Under the same control condition (ADSEQ equal to one), the same digital milliwatt sequence is available to replace received data on any combination of DSTo channels. This is accomplished by setting bit two (RRST) in the Per Time Slot Control Word for the corresponding channel MT9074 Bit 0 RRST RPSIG CC RRST RPSIG - - - . 55 Zarlink Semiconductor Inc. Data Sheet 15 -1). The channels ...
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... Table 18 - Digital Milliwatt Pattern (T1 Zarlink Semiconductor Inc. Data Sheet ...
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... Line Loopback Disable Detect - LLDD - in the Alarm Status Word (bit 0 address 11H of page 3H) will be asserted when a repeating 001 pattern (either framed or unframed) has persisted for 48 milliseconds. Line Loopback Enable Detect LLED in the Alarm Status Word will be asserted when a repeating 00001 pattern (either framed or unframed) has persisted for 48 milliseconds. MT9074 57 Zarlink Semiconductor Inc. Data Sheet ...
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... After a MT9074 reset (RESET pin or RST control bit), all interrupts are masked. All interrupts may be suspended, without changing the interrupt mask words, by making the SPND control bit of page 1, address 1AH high. All interrupts are cleared by forcing the pin TxAO low. MT9074 58 Zarlink Semiconductor Inc. Data Sheet ...
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... BPVO PRBSO PRBSMO Interrupt Mask Word Three Bit JAI 1SECI 5SECI RCRI MT9074 Bit 0 SEI TxSLPI RxSLPI Bit 0 PRBSI PDVI - - - Bit 0 Bit 0 SIGI Bit 0 FATxU RxFf RxOv Bit 0 CEFI YI SLPI Bit 0 PRBSI AUXPI RAII Bit Bit 0 SIGI 59 Zarlink Semiconductor Inc. Data Sheet ...
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... Mb/s transmit data is output on pins TXA and TXB (PLCC pins 37,38 - QFP pins 18,19) with the rising edge of E1.5o. Receive digital data is clocked in on pins RRING and RTIP. This data is clocked in with the rising edge of the input 2.048 Mhz clock MS/FR/E1.5i (PLCC pin 66, QFP pin 63). Coding is optional under software control. MT9074 Bit 0 FATxU RxFf RxOv 60 Zarlink Semiconductor Inc. Data Sheet ...
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... TFSYNIM, MFSYNIM, AISIM, LOSIM, SEIM, TxSLPIM, RxSLPIM FEIM, CRCIM, YELIM, COFAIM, BPVIM, PRBSIM, PDVIM FEOM, CRCOM, OOFOM, COFAOM, BPVOM, PRBSOM, PRBSMFOM,MFOOFOM LCDIM, 1SECIM, 5SECIM, BIOIM, SIGIM NRZ, TxL2-0, REDBL, RES2-0 Table 20 - Master Control 1 (Page 1) (T1) 61 Zarlink Semiconductor Inc. Data Sheet Function SPND, INTA, CNTCLR, SAMPLE, ...
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... D4 Yellow Alarm. When set bit 2 of all DS0 channels are forced low. Transmit All Ones. When low, this control bit forces a framed or unframed (depending on the state of Transmit Alarm Control bit 0) all ones to be transmit at TTIP and TRING. (Page 1, Address 11H) 62 Zarlink Semiconductor Inc. Data Sheet ...
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... Overhead Sbits Override. If set, this bit forces the overhead bits to be inserted as an overlay on any of the following alarm conditions: i) transmit all ones, ii) loop up code insertion, iii) loop down code insertion. (Page 1, Address 11H) Functional Description (Page 1, Address 12H) 63 Zarlink Semiconductor Inc. Data Sheet ...
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... If set to zero the least significant nibble is active for CSTi and CSTo and the most significant nibble of CSTo is tristate. Table 25 - Signaling Control Word (T1) MT9074 Functional Description (Page 1, Address 12H) Functional Description (Page 1, Address 13H) Functional Description (Page 1, Address 14H) 64 Zarlink Semiconductor Inc. Data Sheet ...
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... Per Time Slot Control words - Pages 7 and 8 Address 10H to IFH inclusive) has the same effect as setting control bit RBEn low. Table 26 - Coding and Loopback Control Word (T1)(Page 1, Address 15H) MT9074 Functional Description (Page 1, Address 14H) Functional Description 65 Zarlink Semiconductor Inc. Data Sheet ...
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... Loss of Signal Error Insertion. If one, the MT9074 transmits an all zeros signal (no pulses). Zero code suppression is overridden. If zero, data is transmitted normally. Table 30 - Error Insertion Word (T1) MT9074 Functional Description Table 27 - Reserved (T1) (Page 1, Address 16H) Functional Description Functional Description (Page 1, Address 18H) Functional Description (Page 1, Address 19H) 66 Zarlink Semiconductor Inc. Data Sheet ...
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... This allows for a system design employing a TTL output oscillator as a 20.000 Mhz reference clock. 1 RSV Reserved. Set to zero for normal operation. 0 RSV Reserved. Set to zero for normal operation. Table 31 - Reset Control Word (T1) MT9074 Functional Description (Page 1, Address 19H) Functional Description (Page 1, Address 1AH) 67 Zarlink Semiconductor Inc. Data Sheet ...
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... Psuedo Random Bit Sequence Error Interrupt Mask. When unmasked an interrupt will be generated upon detection of an error with a channel selected for PRBS testing unmasked masked. Table 33 - Interrupt Mask Word One (T1) MT9074 Functional Description (Page 1, Address 1BH) Functional Description (Page 1, Address 1CH 68 Zarlink Semiconductor Inc. Data Sheet ...
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... Multiframes Out Of Sync Overflow Interrupt Mask. When unmasked an interrupt will be generated when the multiframes out of frame counter changes from FFH to 00H unmasked masked. Table 34 - Interrupt Mask Word Two (T1) MT9074 Functional Description (Page 1, Address 1CH Functional Description (Page 1, Address 1DH) 69 Zarlink Semiconductor Inc. Data Sheet ...
Page 70
... Signaling Interrupt Mask. When unmasked an interrupt will be initiated when a change of state (optionally debounced - see DBEn in the Data Link, Signaling Control Word page 1 address 12H) is detected in the signaling bits (AB or ABCD) pattern unmasked masked. (Page 1, Address 1EH) 70 Zarlink Semiconductor Inc. Data Sheet ...
Page 71
... RES2 RES1 RES0 Receive Equalization 0 ÷ ÷ ÷ ÷ > reserved reserved reserved These settings have no effect if REDBL is set to zero. (Page 1, Address 1FH) 71 Zarlink Semiconductor Inc. Data Sheet ...
Page 72
... Set all bits to zero for normal operation. Set all bits to zero for normal operation. Set all bits to zero for normal operation. Set all bits to zero for normal operation. Set all bits to zero for normal operation. CP6-0 CP6-0 CP6-0 CP6-0 72 Zarlink Semiconductor Inc. Data Sheet Names ...
Page 73
... TTST, RRST set. If zero, a PRBS generator / detector will be connected to channels with TTST, RRST respectively. Reserved. Must be kept at 0 for normal operation. (Page 2, Address 10H) (T1) Functional Description (Page 2, Address 11H) (T1) 73 Zarlink Semiconductor Inc. Data Sheet ...
Page 74
... CPL of the Custom Tx Pulse Enable Register - address 11H of Page 2 is set high. Table 42 - Custom Pulse Word 3 MT9074 Functional Description (Page 2, Address 1CH) (T1) Functional Description (Page 2, Address 1DH) (T1) Functional Description (Page 2, Address 1EH) (T1) 74 Zarlink Semiconductor Inc. Data Sheet ...
Page 75
... D4YALM, D4Y48, SECYEL, ESFYEL, BLUE, PDV, LLED, LLDD 1SEC, 2SEC, 5SEC RSLIP, RSLPD, RxFRM RxTS4-0, RxBC2-0 RxBOM7-0 PD4-PD0, LLOS TSLIP, TSLPD, TxSBMSB TxTS4-0, TxBC2 Unused Unused Unused. Internally set to 10101111 Table 44 - Master Status 1 (Page 3) (T1) 75 Zarlink Semiconductor Inc. Data Sheet Function ...
Page 76
... Up to fifteen errors are permitted per integration period. MT9074 Functional Description (Page 3, Address 10H) (T1) Functional Description Yellow Alarm. This bit Table 46 - Alarm Status Word (Page 3, Address 11H) (T1) 76 Zarlink Semiconductor Inc. Data Sheet sets if the ESF yellow alarm ...
Page 77
... Unused Table 48 - Most Significant Phase Status Word MT9074 Functional Description Table 46 - Alarm Status Word (Page 3, Address 11H) (T1) Functional Description Table 47 - Timer Status Word (Page 3, Address 12H) (T1) Functional Description (Page 3, Address 13H) (T1) 77 Zarlink Semiconductor Inc. Data Sheet ...
Page 78
... Functional Description (Page 3, Address 15H) (T1) Functional Description PD3 PD2 PD1 PD0 Line Attenuation less than 4dB 3-8dB 8-14dB 14-20dB more than 20dB (Page 3, Address 16H) (T1) 78 Zarlink Semiconductor Inc. Data Sheet ...
Page 79
... Table 53 - Transmit Slip Buffer Delay Bit Name 7-0 ID7-0 Table 54 - Identification Word MT9074 Functional Description (Page 3, Address 17H) (T1) Functional Description (Page 3, Address 18H) (T1) Functional Description ID Number. Contains device code 10101111 (Page 3, Address 1FH) (T1) 79 Zarlink Semiconductor Inc. Data Sheet ...
Page 80
... Table 55 - Master Status 2 (Page 4) (T1) Functional Description This counter is incremented for each PRBS error detected on any of the receive channels connected to the PRBS error detector. Table 56 - PRBS Error Counter (Page 4, Address 10H) (T1) 80 Zarlink Semiconductor Inc. Data Sheet Function HDLC1I, LCDI, 1SECI, 5SECI, ...
Page 81
... It is cleared after a read. Line Loopback Disable Detect Latch. This bit is set upon receipt of a line loopback disable code cleared after a read. (Page 4, Address 12H) (T1) Functional Description (Page 4, Address 13H) (T1) 81 Zarlink Semiconductor Inc. Data Sheet ...
Page 82
... Address 15H) (T1) Functional Description (Page 4, Address 16H) (T1) Functional Description Least Significant Bits of the BPV Counter. The least significant eight bits bit counter that is incremented once for every bipolar violation error received. (Page 4, Address 17H) (T1) 82 Zarlink Semiconductor Inc. Data Sheet ...
Page 83
... Reading this register clears this bit. MT9074 Functional Description (Page 4, Address 18H) (T1) Functional Description (Page 4, Address 19H) (T1) Functional Description Table 66 - Interrupt Word Zero (Page 4, Address 1BH) (T1) 83 Zarlink Semiconductor Inc. Data Sheet ...
Page 84
... FFH to 00H. Reading this register clears this bit. Table 68 - Interrupt Word Two MT9074 Functional Description (Page 4, Address 1CH) (T1) Functional Description (Page 4, Address 1DH) (T1) 84 Zarlink Semiconductor Inc. Data Sheet ...
Page 85
... Five Second Status Interrupt. When unmasked this interrupt bit goes high whenever the 5 SEC status bit goes from low to high. Reading this register clears this bit. Table 69 - Interrupt Word Three MT9074 Functional Description (Page 4, Address 1DH) (T1) Functional Description (Page 4, Address 1EH) (T1) 85 Zarlink Semiconductor Inc. Data Sheet ...
Page 86
... Multiframes Out Of Sync Overflow Latch. This bit is set when the multiframes out of sync counter overflows cleared after being read. Table 70 - Overflow Reporting Latch MT9074 Functional Description (Page 4, Address 1EH) (T1) Functional Description (Page 4, Address 1FH) (T1) 86 Zarlink Semiconductor Inc. Data Sheet ...
Page 87
... Table 71 describes the bit allocation within each of the 24 active ST-BUS time slots of CSTi. MT9074 Functional Description 87 Zarlink Semiconductor Inc. Data Sheet ...
Page 88
... Remote Time Slot Loopback. If one, the corresponding DS1 receive time slot is looped to the corresponding DS1 transmit time slot. This received time slot will also be present on DSTo. If zero, the loopback is disabled. Table 75 - Per Time Slot Control Words (Pages 7 and 8) (T1) 88 Zarlink Semiconductor Inc. Data Sheet ...
Page 89
... Table 75 - Per Time Slot Control Words (Pages 7 and 8) (T1 Zarlink Semiconductor Inc. Data Sheet - 1) detector ...
Page 90
... ESF superframes. The bits reported may be debounced for milliseconds where control bit DBNCE is set high mode these bits are unused. Table 77 - Receive Channel Associated Signaling (Pages 9 and A) (T1) MT9074 Functional Description 90 Zarlink Semiconductor Inc. Data Sheet ...
Page 91
... CEFIM, YIM, SLPIM FERIM, CRCIM, EBIM, AIS16IM, BPVIM, PRBSIM, AUXPIM & RAI FEOM, CRCOM, EOM, BPVOM, PRBSOM, PRBSMFO JAIM,1SECIM, 5SECIM, RCRIM, SIGIM NRZUNI, REDBL, REMID, REMAX Table 78 - Master Control 1 (Page 1) (E1) 91 Zarlink Semiconductor Inc. Data Sheet Function SPND, INTA, CNTCLR, SAMPLE, ...
Page 92
... Multiframe Reframe. If one, for at least one frame, and then cleared the MT9074 will initiate a search for a new signaling multiframe position. Reframing function is activated on the one to zero transition of the MFRM bit. Table 79 - Mode Selection Control Word (E1) MT9074 Functional Description (Page 1, Address 10H) 92 Zarlink Semiconductor Inc. Data Sheet ...
Page 93
... It is reserved for international use and should normally be kept at one. If CRC processing is used, i.e., CSYN =0, this bit is ignored. Table 81 - HDLC Selection Word (E1) MT9074 Functional Description (Page 1, Address 11H) Functional Description (Page 1, Address 12H) 93 Zarlink Semiconductor Inc. Data Sheet ...
Page 94
... PCM30 signaling multiframe. Table 83 - Interrupt and Signaling Control Word (E1) MT9074 Functional Description (Page 1, Address 12H) Functional Description (Page 1, Address 13H) Functional Description (Page 1, Address 14H) 94 Zarlink Semiconductor Inc. Data Sheet ...
Page 95
... TxCCS (Page 1, Address 14H, bit 5) must be set high, otherwise transmit signaling data, or HDLC1 data will be placed into the outgoing channel 16 timeslot. Table 84 - Coding and Loopback Control Word (E1) MT9074 Functional Description (Page 1, Address 14H) Functional Description (Page 1, Address 15H) 95 Zarlink Semiconductor Inc. Data Sheet ...
Page 96
... Transmit Message Bits The contents of this register are transmit into those outgoing DS1 channels selected by the Per Time Slot Control registers. Table 87 - Transmit Message Word (E1) MT9074 Functional Description (Page 1, Address 16H) Functional Description (Page 1, Address 17H) Functional Description (Page 1, Address 18H) 96 Zarlink Semiconductor Inc. Data Sheet ...
Page 97
... If low, pin LOS will go high when either a loss of signal or a loss of basic frame alignment state exits (bit SYNC on page 03H address 10H is zero). Table 88 - Error Insertion Word (E1) MT9074 Functional Description (Page 1, Address 19H) 97 Zarlink Semiconductor Inc. Data Sheet ...
Page 98
... Alarm Indication Signal Interrupt Mask. When unmasked (AISI=1) a change of state of received AIS will initiate an interrupt unmasked masked. Table 90 - Interrupt Mask Word Zero (E1) MT9074 Functional Description (Page 1, Address 1AH) Functional Description Synchronization Interrupt (Page 1, Address 1BH) 98 Zarlink Semiconductor Inc. Data Sheet Mask. When unmasked ...
Page 99
... unmasked masked. 0 RAIIM Remote Alarm Indication Interrupt Mask. When unmasked (RAII = 1) a received RAI will initiate an interrupt unmasked masked. Table 91 - Interrupt Mask Word One (E1) MT9074 Functional Description (Page 1, Address 1BH) Functional Description (Page 1, Address 1CH) 99 Zarlink Semiconductor Inc. Data Sheet ...
Page 100
... Signaling (CAS) Interrupt Mask. When unmasked and any of the receive ABCD bits of any channel changes state an interrupt is initiated unmasked masked. Table 93 - Interrupt Mask Word Three (E1) MT9074 Functional Description (Page 1, Address 1DH) Functional Description (Page 1, Address 1EH) 100 Zarlink Semiconductor Inc. Data Sheet ...
Page 101
... RES1 RES0 Receive Equalization (Page 1, Address 1FH) 101 Zarlink Semiconductor Inc. Data Sheet Transformer Ratio 0 1:2 0 1:1 15 1:2 12.1 1:2 0 1:2 0 1:1 9.1 1:2 12.1 1:2 0 ÷ ÷ ÷ ÷ >30 dB reserved reserved reserved ...
Page 102
... Set all bits to zero for normal operation. Set all bits to zero for normal operation. Set all bits to zero for normal operation. Set all bits to zero for normal operation. Set all bits to zero for normal operation. CP6-0 CP6-0 CP6-0 CP6-0 102 Zarlink Semiconductor Inc. Data Sheet Names ...
Page 103
... D/A coefficients from the values programmed in the CPW registers. 2-0 RSV Reserved. Must be kept at 0 for normal operation. Table 97 - Custom Tx Pulse Enable MT9074 Functional Description (Page 2, Address 10H) (E1) Functional Description (Page 2, Address 11H) (E1) 103 Zarlink Semiconductor Inc. Data Sheet ...
Page 104
... CPL of the Custom Tx Pulse Enable Register - address 11H of Page 2 is set high. Table 100 - Custom Pulse Word 3 MT9074 Functional Description (Page 2, Address 1CH) (E1) Functional Description (Page 2, Address 1DH) (E1) Functional Description (Page 2, Address 1EH) (E1) 104 Zarlink Semiconductor Inc. Data Sheet ...
Page 105
... RxTS4-0, RxBC2-0 RIU0 &RFA2-8 EQSTAT4-0, LLOS JACS, JACF, JAE, JAF4, JAFC, JAE4, JAF RIU1, RNFAB, RALM, &RNU4-8 RMAI1-4, X1, Y, X2, & X3 RAIS, MFALMS, SLIPS Set to 10101111 Table 102 - Master Status 1 (Page 3) (E1) 105 Zarlink Semiconductor Inc. Data Sheet Function AISS, AIS16S, LOSS, AUXPS, ...
Page 106
... SYNC bit was equal to zero (basic frame alignment has been maintained). If zero, indicates normal operation. Table 104 - Alarm Status Word 1 (Page 3, Address 11H) (continued) (E1) MT9074 Functional Description (Page 3, Address 10H) (E1) Functional Description 106 Zarlink Semiconductor Inc. Data Sheet ...
Page 107
... RCRS RAI and Continuous CRC Error Status. If one, there is currently an RAI and continuous CRC error condition. If zero, normal operation. Updated on a multiframe basis. Table 104 - Alarm Status Word 1 (Page 3, Address 11H) (continued) (E1) MT9074 Functional Description 107 Zarlink Semiconductor Inc. Data Sheet ...
Page 108
... Timer Two. This bit will be high when the MT9074 acquires terminal frame synchronization persisting for 10 msec. This bit shall be low when non-normal operational frames are received. I.431 Section 5.9.2.2.3. Table 105 - Timer Status Word MT9074 Functional Description (Page 3, Address 12H) (E1) 108 Zarlink Semiconductor Inc. Data Sheet ...
Page 109
... ST-BUS read frame boundary. The count is updated every 250 uS. Table 107 - Least Significant Phase Status Word MT9074 Functional Description (Page 3, Address 13H) (E1) Functional Description (Page 3, Address 14H) (E1) 109 Zarlink Semiconductor Inc. Data Sheet ...
Page 110
... Table 109 - Receive Signal Status Word MT9074 Functional Description (Page 3, Address 15H) (E1) Functional Description PD3 PD2 PD1 PD0 Line Attenuation less than 3 8- 14- more than 20 dB (Page 3, Address 16H) (E1) 110 Zarlink Semiconductor Inc. Data Sheet ...
Page 111
... Receive National Use Four to Eight. These bits are received on the PCM30 2048 kbit/sec. link in bit positions four to eight (the Sa bits) of the non-frame alignment signal. Table 111 - Receive Non-Frame Alignment Signal MT9074 Functional Description (Page 3, Address 17H) (E1) Functional Description (Page 3, Address 18H) (E1) 111 Zarlink Semiconductor Inc. Data Sheet ...
Page 112
... If zero, auxiliary pattern is not being received. This pattern will be decoded in the presence of a bit error rate of as much as 10-3. Table 113 - Alarm Status Word 2 (Page 3, Address 1BH) (E1) MT9074 Functional Description (Page 3, Address 19H) (E1) Functional Description 112 Zarlink Semiconductor Inc. Data Sheet ...
Page 113
... Unused. Table 113 - Alarm Status Word 2 (Page 3, Address 1BH) (E1) Bit Name 7-0 ID7-0 Table 114 - Identification Word (Page 3, Address 1FH) (E1) MT9074 Functional Description Functional Description ID Number. Contains device code 10101111 113 Zarlink Semiconductor Inc. Data Sheet ...
Page 114
... PRBSMFOFOL Table 115 - Master Status 2 (Page 4) (E1) Functional Description This counter is incremented for each PRBS error detected on any of the receive channels connected to the PRBS error detector. Table 116 - PRBS Error Counter (Page 4, Address 10H) (E1) 114 Zarlink Semiconductor Inc. Data Sheet Function ...
Page 115
... It is cleared when the register is read. Unused. (Page 4, Address 12H) (E1) Functional Description Errored FAS Counter bit counter that is incremented once for every receive frame alignment signal that contains one or more errors. (Page 4, Address 13H) (E1) 115 Zarlink Semiconductor Inc. Data Sheet ...
Page 116
... Address 17H) (E1) Functional Description Unused CRC-4 Error Counter These are the most significant eight bits of the CRC-64error counter. (Page 4, Address 18H) (E1) 116 Zarlink Semiconductor Inc. Data Sheet ...
Page 117
... Reading this register clears this bit. Receive SLIP Interrupt. When unmasked this interrupt bit goes high whenever a controlled frame slip occurs in the receive elastic buffer. Reading this register clears this bit. (Page 4, Address 1BH) (E1) 117 Zarlink Semiconductor Inc. Data Sheet Alignment Interrupt. When ...
Page 118
... Reading this register clears this bit. Remote alarm Indication Interrupt. When unmasked this interrupt bit goes high whenever the bit 3 of non-frame alignment signal is high. Reading this register clears this bit. (Page 4, Address 1CH) (E1) 118 Zarlink Semiconductor Inc. Data Sheet ...
Page 119
... FFH to 00H. Reading this register clears this bit. Pseudo Random Bit Sequence Multiframe Counter Overflow Interrupt. When unmasked this interrupt bit goes high whenever the multiframe counter attached to the PRBS error counter overflows. FFH to 00H unmasked masked. Unused (Page 4, Address 1DH) (E1) 119 Zarlink Semiconductor Inc. Data Sheet ...
Page 120
... Signaling Interrupt. When unmasked this interrupt bit goes high whenever a change of state (optionally debounced - see DBEn in the Data Link, Signaling Control Word) is detected in the signaling bits (AB or ABCD) pattern. Reading this register clears this bit. (Page 4, Address 1EH) (E1) 120 Zarlink Semiconductor Inc. Data Sheet ...
Page 121
... Table 130 - Overflow Reporting Latch (Page 4, Address 1FH) (E1 121 Zarlink Semiconductor Inc. Data Sheet ...
Page 122
... Table 134 - Mapping to CEPT Channels(Page 8H and 9H) (E1) MT9074 Functional Description Functional Description 122 Zarlink Semiconductor Inc. Data Sheet ...
Page 123
... Zarlink Semiconductor Inc. Data Sheet ...
Page 124
... Link in bit positions one to four of time slot 16 in frame n B(n), (where 15), and are the signaling bits associated with channel n. C(n), D(n) Table 138 - Receive CAS Channels (CSTo) (E1) MT9074 Functional Description Functional Description 124 Zarlink Semiconductor Inc. Data Sheet ...
Page 125
... CRC15-CRC8 Rx CRC LSB CRC7-CRC0 --- TxCNT7-0 --- HRST, ARTST, HLOOP Test Status RxCLK, TxCLK, VCRC, VADDR --- RSV, RFD2-0,RSV, TFD2-0 --- RSV, RFFS2-0, RSV, TFLS2-0 125 Zarlink Semiconductor Inc. Data Sheet Function RxEN, TxEN, EOP, FA, Idle-Chan, RQ9, RQ8, CYCLE, TxCRCI, FA:TxUNDERIM, RxFFIM, RxEOP, TxEOP, ...
Page 126
... FA), and the resulting 10 bit word is written to the TX FIFO. The FIFO status is not changed immediately after a write or read occurs updated after the data has settled and the transfer to the last available position has finished. (Page B & C, Address 12H) 126 Zarlink Semiconductor Inc. Data Sheet ...
Page 127
... FRUN When high the HDLC TX and RX are continuously enabled providing the RxEN and TxEN bits are Table 144 - HDLC Control register 1 MT9074 Functional Description (Page B & C, Address 12H) Functional Description set. (Page B & C, Address 13H) 127 Zarlink Semiconductor Inc. Data Sheet ...
Page 128
... The number of bytes in the RX FIFO is less than the interrupt threshold level FIFO full. 1 The number of bytes in the RX FIFO has reached or exceeded the interrupt threshold level. Table 145 - HDLC Status Register (Page B & C Address 14H) 128 Zarlink Semiconductor Inc. Data Sheet ...
Page 129
... Interrupt Register. An interrupt is disabled when the microprocessor writes a RxFEIM bit in this register. TxFLIM This register is cleared on power reset. FA:TxUNDERIM RxFFIM RxOVFIM Table 147 - HDLC Interrupt Mask Register MT9074 Functional Description (Page B & C, Address 15H) Functional Description (Page B & C, Address 16H) 129 Zarlink Semiconductor Inc. Data Sheet ...
Page 130
... The receiver will be re-enabled upon detection of the next flag, but will overflow again unless the RX FIFO is read. This bit is reset after a read. (Page B & C, Address 17H) Functional Description (Page B & C, Address 18H) 130 Zarlink Semiconductor Inc. Data Sheet ...
Page 131
... After testing is enabled, serial data is clocked in until the data aligns with the internal comparison (16 RXC clock cycles) and then the clock is stopped. The expected pattern is F0B8 hex. Each bit of the CRC can be corrupted to allow more efficient testing. (Page B & C, Address 1BH) 131 Zarlink Semiconductor Inc. Data Sheet ...
Page 132
... Valid Address. This is the address recognition status bit for the receiver. Data is clocked into the Address Recognition Register and then this bit is monitored to see if comparison was successful (bit will be high). (Page B & C, Address 1CH) 132 Zarlink Semiconductor Inc. Data Sheet ...
Page 133
... TFD2 TFD1 TFD0 (Page B & C, Address 1DH) 133 Zarlink Semiconductor Inc. Data Sheet Full Status Level 112 128 Full Status Level 112 128 ...
Page 134
... RX FIFO Full Interrupt threshold Level 104 1 0 112 1 1 120 TFLS1 TFLS0 TX FIFO Low Interrupt threshold Level 134 Zarlink Semiconductor Inc. Data Sheet ...
Page 135
... 135 Zarlink Semiconductor Inc. Data Sheet Min. Max. Units - -65 150 °C Units Test Conditions °C V Units Test Conditions mA Outputs unloaded. Transmitting an all 1’s signal ...
Page 136
... CSH t 15 RWH t 15 ADH t 90 DDR t 90 DHR t 90 DAZ t 15 DSW t 15 DHW 136 Zarlink Semiconductor Inc. Data Sheet Conditions/Notes See Note 1 See Note 1 TTL CMOS TTL CMOS Test Conditions = =50 pF ...
Page 137
... RDL t 60 RDH t 0 CSS t 0 CSH t 10 ADS t 15 ADH t 90 DDR t 90 DAZ t 15 DSW t 15 DHW 137 Zarlink Semiconductor Inc. Data Sheet CSH RWH ADH DAZ DHR DHW V TT Units Test Conditions ...
Page 138
... TCLK t 40 TCLKL t 40 TCLKH t 12 DISU t 12 DIH t 12 MSSU t 12 MSH t DOD t 25 TRST 138 Zarlink Semiconductor Inc. Data Sheet t CSH t CSH t ADH t ADH t DAZ t t DSW DHW Max. Units Test Conditions ns BSDL spec’s 12 MHz ...
Page 139
... MT9074 t msh t dih t disu t dod Figure 18 - JTAG Port Timing Sym. Min. Typ. t 324 TDS t 35 TDH DLH DLS 139 Zarlink Semiconductor Inc. Data Sheet t tclk t t tclkl tclkh t trst Max. Units Test Conditions ns 150 TT ...
Page 140
... Figure 21 - Transmit Data Link Functional Timing (E1 mode) MT9074 Sym. Min. Typ. Max. t 244 TDC t 35 TDS t 35 TDH t TDC t t DLH DLS Example kb/s Example kb/s 140 Zarlink Semiconductor Inc. Data Sheet Units Test Conditions ns 150 TT ...
Page 141
... RxFP t RFD E1.5o RxDLCLK t RDD RxDL Figure 23 - Receive Data Link Diagram (T1 mode) MT9074 Sym. Min. Typ. t RDC t RDD t RFD t RFD t RDC 141 Zarlink Semiconductor Inc. Data Sheet Max Units Test Conditions 160 TT TT ...
Page 142
... Figure 25 - Receive Data Link Timing Diagram (E1 mode) MT9074 Sym. Min. Typ. Max. Units t 160 RDC t 45 RDD t 45 RFD Example kb/s Example kb/s t RDC 142 Zarlink Semiconductor Inc. Data Sheet Test Conditions TT TT, CT ...
Page 143
... FDP Channel 0 Channel 0 Bit 7 Bit 6 Bit Cell Bit Cell t FPH t FPS t 4WI t SIH t SIS t SOD 143 Zarlink Semiconductor Inc. Data Sheet Units Test Conditions ns Line Synchronization Mode 150 pF ns Line Synchronous Mode Channel 0 Bit 4WI V TT ...
Page 144
... SIS SOD Sym. Min. Typ. Max MOD Bit 4 Bit 0 Bit 7 Bit 6 144 Zarlink Semiconductor Inc. Data Sheet TT, CT Units Test Conditions ns 150 256 C2 periods -100 nsec Frame 0 Bit 5 Bit 4 Bit 0 Bit 7 ...
Page 145
... Note : These two signals do not have a defined phase relationship Figure 31 - Multiframe Timing Diagram (T1 mode or E1 mode) MT9074 Frame N Bit 4 Bit 0 Bit 7 Bit 6 t MOD t MH 145 Zarlink Semiconductor Inc. Data Sheet Frame 0 Bit 5 Bit 4 Bit 0 Bit TT, t MH2 ...
Page 146
... RxA/B Figure 33 - Receive Digital Data Timing Diagram (LIU Disabled) MT9074 Sym. Min. Typ. Max. t 648 DW t 244 RDS RDH 146 Zarlink Semiconductor Inc. Data Sheet Units Test Conditions ns 150 mode ns 150 mode ns ...
Page 147
... Bit Bit Bit Bit Bit Bit (8/2.048) µs Figure 35 - PCM30 Format 147 Zarlink Semiconductor Inc. Data Sheet Max. Units Test Conditions ns ns Frame Frame Channel Channel 23 24 Least Bit Bit ...
Page 148
... Most Bit Significant 7 Bit (First) Figure 36 - ST-BUS Stream Format MT9074 125µs Channel • • • 30 Bit Bit Bit Bit Bit (8/2.048)µs 148 Zarlink Semiconductor Inc. Data Sheet Channel Channel 31 0 Least Bit Bit Significant 0 1 Bit (Last) ...
Page 149
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Page 150
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Page 151
... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...