zl50064 Zarlink Semiconductor, zl50064 Datasheet - Page 20

• Manufacturer Part Number: zl50064
• Description: 16 K Channel Digital Switch With High Jitter Tolerance, Single Rate 2, 4, 8 Or 16 Mbps And 64 Input And 64 Output Streams
• Manufacturer: Zarlink Semiconductor

ZL50062/4
Data Sheet
2.1.6.2
Backplane Output Port
Operation of stream data in Connection Mode or Message Mode is determined by the state of the BMM bit of the
Backplane Connection Memory and the channel high impedance state is controlled by the BE bit of the Backplane
Connection Memory. The data source (i.e. from the Local or Backplane Data Memory) is determined by the BSRC
bit of the Backplane Connection Memory. Refer to Section 8.2, Backplane Connection Memory and Section 11.4,
Backplane Connection Memory Bit Definition for more details.
2.2
Frame Pulse Input and Master Input Clock Timing
The input frame pulse (FP8i) is an 8kHz input signal active for 122ns or 244ns at the frame boundary. The FPW bit
in the Control Register must be set according to the applied pulse width. See Pin Description and Table 13, “Control
Register Bits” on page 37, for details.
The active state and timing of FP8i can conform either to the ST-BUS or to the GCI-Bus as shown in Figure 7,
ST-BUS and GCI-Bus Input Timing Diagram for Different Data Rates. The ZL50062/64 device will automatically
detect whether an ST-BUS or a GCI-Bus style frame pulse is being used for the master frame pulse (FP8i). The
output frame pulses (FP8o and FP16o) are always of the same style (ST-BUS or GCI-Bus) as the input frame
pulse. The active edge of the input clock (C8i) shall be selected by the state of the Control Register bit C8IPOL.
Note that the active edge of ST-BUS is falling edge, which is the default mode of the device, while GCI-Bus uses
rising edge as the active edge. Although GCI frame pulse will be automatically detected, to fully conform to
GCI-Bus operation, the device should be set to use C8i rising edge as the active edge (by setting bit C8IPOL HIGH)
when GCI-Bus is used.
For the purposes of describing the device operation, the remaining part of this document assumes the ST-BUS
frame pulse format with a single width frame pulse of 122ns and a falling active clock-edge, unless explicitly stated
otherwise.
In addition, the ZL50062 device provides FP8o, FP16o, C8o and C16o outputs to support external devices which
connect to the output ports. The ZL50064 only provides FP8o and C8o outputs. The generated frame pulses (FP8o,
FP16o) will be provided in the same format as the master frame pulse (FP8i). The polarity of C8o and C16o, at the
frame boundary, can be controlled by the Control Register bit, COPOL. An analog phase lock loop (APLL) is used
to multiply the input clock frequency on C8i to generate an internal clock signal operating at 131.072MHz.
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