zl50064 Zarlink Semiconductor, zl50064 Datasheet - Page 63
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zl50064
Manufacturer Part Number
zl50064
Description
16 K Channel Digital Switch With High Jitter Tolerance, Single Rate 2, 4, 8 Or 16 Mbps And 64 Input And 64 Output Streams
Manufacturer
Zarlink Semiconductor
Datasheet
1.ZL50064.pdf
(68 pages)
- Current page: 63 of 68
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Non-Multiplexed Microprocessor Port Timing
Note 1:
Note 2:
10
12
11
1
2
3
4
5
6
7
8
9
CS setup from DS falling
R/W setup from DS falling
Address setup from DS falling
CS hold after DS rising
R/W hold after DS rising
Address hold after DS rising
Data setup from DTA Low on Read
Data hold on read
Data setup on write
Data hold on write
Acknowledgment Delay:
Acknowledgment Hold Time
High Impedance is measured by pulling to the appropriate rail with R
C
There must be a minimum of 30ns between CPU accesses, to allow the device to recognize the accesses as separate (i.e., a
minimum of 30ns must separate the de-assertion of DTA (to high) and the assertion of CS and/or DS to initiate the next
access).
Reading/Writing Registers
Reading/Writing Memory
L
.
Characteristics
Zarlink Semiconductor Inc.
t
t
Sym
t
t
t
t
t
t
t
t
t
t
RWS
RWH
WDS
WDH
ZL50062/4
RDH
CSS
ADS
CSH
ADH
RDS
AKD
AKH
63
Min
12
0
9
9
0
9
9
5
9
9
L
, with timing corrected to cancel time taken to discharge
Typ
Max
4.5
88
80
11
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Memory Read
Register Read
C
C
Note 1
C
C
C
Note 1
Test Conditions
L
L
L
L
L
=60pF
=60pF, R
=60pF
=60pF
=60pF, R
Data Sheet
L
L
=1k
=1k,
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