zl50064 Zarlink Semiconductor, zl50064 Datasheet - Page 44

• Manufacturer Part Number: zl50064
• Description: 16 K Channel Digital Switch With High Jitter Tolerance, Single Rate 2, 4, 8 Or 16 Mbps And 64 Input And 64 Output Streams
• Manufacturer: Zarlink Semiconductor

13.4
Addresses 0063
There are thirty-two Backplane Input Delay Registers (BIDR0 to BIDR31).
When the SMPL_MODE bit in the Control Register is LOW, the input data sampling point defaults to the 3/4 bit
location and BIDR0 to BIDR31 define the input bit and fractional bit delay of each Backplane stream. The possible
bit delay adjustment is up to 7
When the SMPL_MODE bit is HIGH, BIDR0 to BIDR31 define the input bit sampling point as well as the integer bit
delay of each Backplane stream. The input bit sampling point can be adjusted in 1/4 bit increments. The bit delay
can be adjusted in 1-bit increments from 0 to 7 bits.
The BIDR0 to BIDR31 registers are configured as follows:
(where n = 0 to 31)
Backplane Input Bit Delay Registers (BIDR0 to BIDR31)
BIDRn Bit
LID4
Table 16 - Local Input Bit Delay and Sampling Point Programming Table (continued)
1
1
1
1
15:5
4:0
H
to 0082
LID3
1
1
1
1
Table 17 - Backplane Input Bit Delay Register (BIDRn) Bits
H
3
LIDn
LID2
/
4
1
1
1
1
Reserved
bits, in steps of
BID[4:0]
Name
LID1
0
0
1
1
Reset
Value
Zarlink Semiconductor Inc.
0
0
1
ZL50062/4
LID0
/
4
0
1
0
1
bit.
Reserved
Must be set to 0 for normal operation
Backplane Input Bit Delay Register
When SMPL_MODE = LOW, the binary value of these
bits refers to the input bit and fractional bit delay value (0
to 7
When SMPL_MODE = HIGH, the binary value of BID[1:0]
refers to the input bit sampling point (
refer to the integer bit delay value (0 to 7 bits).
44
SMPL_MODE
3
Input Data
/
Bit Delay
4
= LOW
).
7 1/4
7 1/2
7 3/4
7
Input Data
Bit Delay
Description
7
7
7
7
SMPL_MODE
= HIGH
Input Data
1
Sampling
/
4
Point
to
3/4
4/4
1/4
2/4
4
/
4
Data Sheet
). BID[4:2]