zl50031 Zarlink Semiconductor, zl50031 Datasheet - Page 15

• Manufacturer Part Number: zl50031
• Description: Flexible 4 K X 2 K Channel Digital Switch With H.110 Interface And 2 K X 2 K Local Switch
• Manufacturer: Zarlink Semiconductor

5.0
The local input delay selection allows individual local input streams to be aligned and shifted against the input frame
pulse (FRAME_A_io or FRAME_B_io). This feature compensates for the variable path delays in the local interface.
Such delays can occur in large centralized and distributed switching systems.
Each local input stream can have its own bit delay offset value by programming the local input bit delay selection
registers (LIDR0 to LIDR5). See Table 11, "Local Input Bit Delay Registers (LIDR0 to LIDR5) Bits" on page 39, for
the contents of these registers. Possible bit adjustment can range up to +7
1/4
6.0
The ZL50031 allows users to advance individual backplane or local output streams with respect to the frame
boundary. This feature is useful in compensating for variable output delays caused by various output loading
conditions. Each output stream can have its own advancement value programmed by the output advancement
registers. The backplane output advancement registers (BOAR0 to BOAR3) are used to program the backplane
output advancement. The local output advancement registers (LOAR0 to LOAR1) are used to program the local
output advancement. Possible adjustment for local and backplane output data streams is 22.5 ns with a resolution
of 7.5 ns. The advancement is independent of the output data rate. Table 13 on page 41 and Figure 13, "Example
of Backplane Output Advancement Timing" on page 41, and Table 14 on page 42 and Figure 14, "Local Output
Advancement Timing" on page 42 describe the details of the output advancement programming for the backplane
and local interfaces respectively.
7.0
The output data of the ZL50031’s local side is slightly advanced with respect to the frame and bit boundary as
defined by the local output clocks and frame pulses (ST_FPo0, ST_CKo0, ST_FPo1, ST_CKo1). The advancement
is in the range of 5 ns to 17 ns. Despite this advancement, the ZL50031 will operate within the parameters specified
in the datasheet because input data are usually sampled at the 3/4 or 1/2 point of the bit cell. However, the user
should be cautious when introducing additional delay to the clock signals only (e.g., by passing them through glue
logic, FPGA, or CPLD), which will introduce a few nanoseconds of delay relative to the data. If the clock signal is
delayed, data will be advanced from the receiver device’s point of view. This may cause errors in sampling the data.
Using an example where a 3/4 sampling point is used, there is about 30 ns from the sampling point to the end of the
bit cell. With a worst-case of 17 ns advancement, the timing margin will be approximately 13 ns. Any additional
delays applied to the local output clocks (ST_CKo0 and ST_CKo1) must not exceed 13 ns minus the hold time of
the receiving device. Delays applied to both clocks and data equally will not impact the device operation.
bit period. See Table 12 on page 39 and Figure 12 on page 40 for local input delay programming.
Local Input Delay Selection
Output Advancement Selection
Local Output Timing Considerations
Table 5 - Mode Selection for Local LSTi12 - 15 and LSTo12 - 15 Streams, Group 3
LG31
0
0
1
1
DMS Register Bits
LG30
0
1
0
1
Zarlink Semiconductor Inc.
ZL50031
8.192 Mbps
4.096 Mbps
2.048 Mbps
Reserved
Modes
15
3/4
LSTi12-15, LSTo12-15
bit periods forward with resolution of
Usable Streams
Data Sheet