zl50031 Zarlink Semiconductor, zl50031 Datasheet - Page 24

• Manufacturer Part Number: zl50031
• Description: Flexible 4 K X 2 K Channel Digital Switch With H.110 Interface And 2 K X 2 K Local Switch
• Manufacturer: Zarlink Semiconductor

16.2
The DPLL has four different modes to handle reference failure. These modes are selected by the FDM0 and FDM1
bits of the DOM2 Register. If FDM1-0 is ’10’ then the Primary reference is always used regardless of failures. If
FDM1-0 is ’11’ then the Secondary reference is always used regardless of failures. Otherwise the DPLL operates in
one of two failure detection modes: Autodetect or Manual detection mode. When the FDM0 and FDM1 bits are set
to low in the DOM2 register (‘00’), the DPLL is in the Autodetect Mode. In this mode, the outputs from the
Reference Monitor Circuits LOS_PRI and LOS_SEC are used by the State Machine Circuit. When the FDM0 bit is
set to high and FDM1 bit is set to low (‘01’), the DPLL is in the Manual Detection Mode and the LOS_PRI and
LOS_SEC signals are selected from the PRI_LOS and SEC_LOS input pins to be used by the State Machine
Circuit. See Table 20 on page 47 for selection of the Failure Detection Modes.
16.3
When the “A Clocks” or the “B Clocks” are selected as the input reference, an 8.192 MHz clock (either C8_A_io or
C8_B_io) is provided to be the input reference to the PLL circuit. Because the output frame pulse (CT_FRAME)
must be aligned with the selected input frame pulse, the appropriate frame pulse (either FRAME_A_io or
FRAME_B_io) is selected in the Frame Select MUX circuit to be the input of the PLL circuit.
16.4
The CT Clock and Frame Monitor circuits check the period of the C8_A_io and the C8_B_io clocks and the
FRAME_A_io and FRAME_B_io frame pulses. According to the H.110 specification, the C8 period is 122 ns with a
tolerance of +/-35 ns measured between rising edges. If C8 falls outside the range of [87 ns,157 ns], the clock is
rejected and the fail signal (FAIL_A or FAIL_B) becomes high. The Frame pulse period is measured with respect to
the C8 clock. The frame pulse period must have exactly 1024 C8 cycles. Otherwise, the fail signal (FAIL_A or
FAIL_B) becomes high. When the CT BUS clock and frame pulse signals return to normal, the FAIL_A or FAIL_B
signal returns to logic low.
16.5
There are two Reference Monitor Circuits: one for the primary reference (PRI_REF) and one for the secondary
reference (SEC_REF). These two circuits monitor the selected input reference signals and detect failures by setting
up the appropriate fail outputs (SLS and PLS bits in the DHKR register, seeTable 23 on page 50). These fail signals
are used in the Autodetect mode as the LOS_PRI and LOS_SEC signals to indicate when the reference has failed.
The method of generating a failure depends on the selected reference.
When the selected reference frequency is 8.192 MHz (“A Clocks” or “B Clocks”), the fail signals are passed through
from the CT Clock and Frame Monitor circuit outputs FAIL_A and FAIL_B, and used directly to set the SLS and PLS
bits, accordingly.
For all other reference frequencies (8 kHz, 1.544 MHz and 2.048 MHz), the following checks are performed:
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These reference signal verifications include a complete loss or a large frequency shift of the selected reference
signal. When the reference signal returns to normal, the LOS_PRI and LOS_SEC signals will return to logic low.
For all references, the “minimum 90 ns” check is done. This is required by the H.110 specifications - both low
level and high level of the reference must last for minimum 90 ns each.
The “period in the specified range” check is done for all references. The length of the period of the selected
input reference is checked to verify if it is in the specified range. For the E1 (2.048 MHz clock) or the T1
(1.544 MHz clock) reference, the period of the clock can vary within the range of 1 +/- 1/4 of the defined
clock period which is 488 ns for the E1 clock and 648 ns for T1 clock. For the 8 kHz reference, the variation
is from 1 +/- 1/32 period.
If the selected reference is E1 or T1, “64 periods in the specified range” check is done. The selected
reference is observed for a long period (64 reference clock cycles) and checked to verify if it is within the
specified range - from 62 to 66 clock periods.
PRI and SEC MUX Circuits
Frame Select MUX
CT Clock and Frame Monitor Circuits
Reference Monitor Circuits
Zarlink Semiconductor Inc.
ZL50031
24
Data Sheet