am79d2251 Advanced Micro Devices, am79d2251 Datasheet - Page 7

• Manufacturer Part Number: am79d2251
• Description: Dual Intelligent Subscriber Line Audio-processing Circuit Islac
• Manufacturer: Advanced Micro Devices

PIN DESCRIPTIONS
AGND1,
AGND2
DCLK/S0
DGND1–
DGND2
DIO/S1
DRA/DD
DXA/DU
FS/DCL
INT/S2
IREF
LD1–LD2
MCLK
PCLK/FS
P1–P3
Pin
Analog Ground
Data Clock/GCI
Address Strap 0
Digital Ground
Data I/O/GCI Address
Strap 1
RX Path A Backplane
Data/ GCI data
Downstream, Receive
Path B backplane data
TX Path A Backplane
Data/GCI Data
Upstream, TX Path B
Backplane Data
Frame sync/GCI
Downstream Clock
Interrupt/GCI Address
Strap 2
Current Reference
Register Load
Master Clock
PCM Clock/Frame
Sync
ISLIC Control
Pin Name
I/O
I/O
O
O
O
O
O
I
I
I
I
I
I
Analog circuitry ground returns
Provides data control for MPI interface control. For GCI operation, this pin is device address
bit 0. 5 V tolerant.
Digital ground returns
For PCM backplane operation, control data is serially written into and read out of the ISLAC
device via the DIO pin with the MSB first. The data clock (DCLK) determines the data rate.
DIO is high impedance except when data is being transmitted from the ISLAC device under
control of CS/RST. For GCI operation, this pin is device address bit 1. 5 V tolerant.
For the PCM highway, the receive PCM data is input serially through the DRA ports. The
data input is received every 125 µs and is shifted in, MSB first, in 8-bit PCM or 16-bit linear
bursts at the PCLK rate. The receive port can receive information for direct control of the
ISLIC device. This mode is selected in Device Configuration Register 2 (RTSEN = 1,
RTSMD = 1). When selected, this data is received in an independently programmable
timeslot from the PCM data. For the GCI mode, downstream receive and control data is
accepted on this pin. 5 V tolerant.
For the PCM highway, the transmit PCM data is transmitted serially through the DXA port.
The transmission data output is available every 125 µs and is shifted out, MSB first, in 8-bit
PCM or 16-bit linear bursts at the PCLK rate. DXA is high impedance between bursts and
while the device is in the inactive mode. Can also select a mode (RTSEN = 1, RTSMD = 1
or 0 in Device Configuration Register 2) that transmits the Signaling Register MSB contents
first, in an independently programmable timeslot from the PCM data. This data is transmitted
in all modes except disconnect. For the GCI mode, upstream transmit and signaling data is
transferred on this pin. 5 V tolerant.
For PCM operation, pin is Frame Sync. PCM operation is selected by the presence of an
8 kHz Frame Sync signal on this pin in conjunction with the PCLK on the PCLK/FS pin
(see below). This 8 kHz pulse identifies the beginning of a frame. The ISLAC device
references individual timeslots with respect to this input, which must be synchronized to
PCLK. GCI operation is selected by the presence of the downstream clock DCL, on this
pin in conjunction with the presence of a FS on the PCLK/FS pin. In GCI mode, the rate
at which data is shifted into or out of the PCM ports is a derivative of this DCL clock as
selected in Device Configuration Register 1. 5 V tolerant.
For PCM operation, when a subscriber line requires service, this pin goes to a logic 0 to
interrupt a higher level processor. Several registers work together to control operation of
the interrupt: Signaling and Global Interrupt Registers with their associated Mask
Registers, and the Interrupt Register. See the description at configuration register 6 (Mask)
for operation. Logic drive is selectable between open drain and TTL-compatible outputs.
The S2 function is only available on the dual ISLAC device. For GCI operation, it is the
device address bit 2.
External resistor (RREF) connected between this pin and analog ground generates an
accurate, on-chip reference current for the A/D's and D/A's on the ISLAC chip.
The LD pins output 3-level voltages. When LDn is a logic 0, the destination of the code on
P1–P3 is the relay control latches in the ISLIC control register. When LDn is a logic 1, the
destination of P1–P3 is the mode control latches. LDn is driven to VREF when the contents
of the ISLIC control register must not change.
For PCM backplane operation, a DSP master clock connects here. A signal is required
only for PCM backplane operation when PCLK is not used as the master clock. MCLK can
be a wide variety of frequencies. Upon initialization the MCLK input is disabled, and relevant
circuitry is driven by a connection to PCLK. The MCLK connection may be re-established
under user control. 5 V tolerant.
For PCM operation, this is PCM Clock. PCM operation is selected by the presence of a
PCLK signal on this pin in conjunction with the FS on the FS/DCL pin (see below). For
PCM backplane operation, connect a data clock, which determines the rate at which PCM
data is serially shifted into or out of the PCM ports. PCLK can be any multiple of the FS
frequency. The minimum clock frequency for linear/ companded data plus signaling data
is 256 kHz. For GCI operation, this pin is Frame Sync. The FS signal is an 8 kHz pulse
that identifies the beginning of a frame. The ISLAC device references individual timeslots
with respect to this input, which must be synchronized to DCL. 5 V tolerant.
Control the operating modes of the two ISLIC devices connected to the dual ISLAC device.
Am79D2251
Description
7