s71ws256jc0 Meet Spansion Inc., s71ws256jc0 Datasheet - Page 151

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s71ws256jc0

Manufacturer Part Number
s71ws256jc0
Description
Stacked Multi-chip Product Mcp 128/64 Megabit 8m/4m X 16-bit Cmos 1.8 Volt-only, Simultaneous Read/write, Burst Mode Flash Memory With Cellularram
Manufacturer
Meet Spansion Inc.
Datasheet
Note: Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay. Clock
rates below 50MHz (t
150
DQ[15:0]
LB#/UB#
A[22:0]
ADV#
WAIT
WE#
OE#
CE#
CLK
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V OH
V OL
V OH
V OL
CLK
READ Burst Identified
High-Z
Figure 33.6 Four-word Burst Read Operation—Variable Latency
> 20ns) are allowed as long as t
(WE# = HIGH)
t SP
Address
t CSP
t SP
t SP
t SP
Valid
t CEW
High-Z
t HD
t HD
t HD
t HD
t KHKL
t ABA
t OLZ
A d v a n c e
t ACLK
CellularRAM Type 2
t BOE
t KHTL
t CLK
CSP
OUTPUT
VALID
t KOH
specifications are met.
I n f o r m a t i o n
OUTPUT
VALID
Legend:
t KP
OUTPUT
VALID
Don't Care
t KP
OUTPUT
VALID
CellRam_03_A0 March 9, 2005
t HD
t OHZ
t HZ
t CBPH
Undefined
High-Z

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