m27480 Mindspeed Technologies, m27480 Datasheet - Page 2

• Manufacturer Part Number: m27480
• Description: 3rd Generation Traffic Stream Processor ?tsp3
• Manufacturer: Mindspeed Technologies

3rd Generation Traffic Stream Processor
Flexible Communications Processing Power
The foundation of the M27480 TSP3 architecture is based on
a single programmable Octave™ microprocessor core with
several hardware co-processing engines controlled by software.
This provides a powerful architectural advantage by combining
the distinct benefits associated with both software-based
(programmability) and fixed-function (wire-speed) devices.
The Octave processor is a 32-bit RISC engine, optimized to
meet the demands of traffic stream processing. The proces-
sor is tightly coupled to surrounding hardware and the data
path through register and instruction sets providing efficient
dispatching of parallel hardware operations while performing
traffic stream processing functions. The Octave processor
extends the familiar RISC instruction set with specialized
instructions for interworking and traffic management.
The architecture is equally adept at handling packets and cells
and can be used for processing single-service or multiple
service applications concurrently.
Hardware Accelerated Architecture
Multiple hardware engines are integrated on-chip with a
single Octave processor to achieve high performance network
processing. The input data path streams into the M27480
through “universal-link” receive ports, Ethernet, and/or PCI-
mapped FIFOs. Data path and host configurations are highly
flexible. The multi-protocol channel descriptor look-up engine
(CDL) classifies and maps each traffic stream to an Octave
software process by examining header fields and converting
the traffic stream into an internal data format. Example clas-
sifications performed by the CDL include Ethernet MAC,
stacked VLAN tags, ATM VCI/VPI, MPLS EXP and IP (Layer 3 & 4
– such as DHCP snooping, UDP, DSCP, etc.).
All traffic streams flow throughout the context cache and
data RAM (CCR). The Octave processor has very low-latency
access to this memory and it is here that internetworking
1,281 to 32K
c c o o n n n n e e c c t t i i o o n n s s
up to 1,280
p p r r o o c c e e s s s s i i n n g g t t h h r r o o u u g g h h p p u u t t
470+ Mpbs/560+Kpps
1.5+ Gbps, 1.9+ Mpps
functions can inspect and modify the traffic stream. Per-
stream context, or state, is pre-fetched and loaded into
CCR enabling single-cycle context switching to the next event
by the Octave processor. The Octave processor uses the inte-
grated buffer-management engine (BME) to efficiently
manage memory allocation.
for low-cost DDR SDRAM, an I
and a glueless interface to an optional external CAM for
extending the device’s classification capabilities. The SDRAM
provides buffer storage as well as channel context storage.
However, for applications using up to 1280 channels, an inter-
nal channel context SRAM is provided to boost application
performance by over 3x for up to 1,280 conections. Five inde-
pendent DMA engines work concurrently to sustain high
throughput of stream data and context through an internal
high-speed crossbar memory controller. The device feeds
each output port with a prioritized, wire-speed stream of
data. Up to 64 multi-rate PHY’s can be supported without
head-of-line-blocking. The M27480’s traffic scheduling system
(TSS) makes bandwidth reservations and resolves scheduling
conflicts based on per-stream as well as network path and
tunnel parameters. It may also be used as a system resource
for setting-up complex event timers. Along with the Octave
processor, the TSS can be used to develop unique customizable
scheduling algorithms and hierarchical shaping & scheduling
schemes.
Development Tools
Mindspeed supplies an evaluation board, host driver code and
extensive system development tools supporting customers
using either production binary firmware products, such as
PortMakerIII-AAL5™, or foundation source firmware products,
such as BroadbandMaker™. The TSP3 board development kit
(BDK) provides a chip model, test bench, and diagnostic code
for hardware design verifications. The software development
kit (SDK) is a powerful development environment for customers
modifying TSP3 source code products or developing custom
applications. Mindspeed consulting services are also available
to design, implement, and/or test custom features or stand-
alone applications.
The M27480 provides three external memory interfaces: one
2
C interface for a boot EEPROM,