mh1020 Music Semiconductors, Inc., mh1020 Datasheet - Page 13

• Manufacturer Part Number: mh1020
• Description: Hla Packaged Asynchronous Data Recognition And Recall Processor
• Manufacturer: Music Semiconductors, Inc.

Comparand Register (CR)
The 64-bit Comparand register is the default destination
for data writes and reads, using the Segment Control
register to select which 16-bit segment of the Comparand
register is to be loaded or read out. The persistent source
and destination for data writes and reads can be changed to
the Mask registers or memory by SPS and SPD
instructions. During an automatic or forced compare, the
Comparand register is simultaneously compared against
the CAM portion of all memory locations with the correct
validity condition. Automatic compares always compare
against valid memory locations, while forced compares,
using CMP instructions, can compare against memory
locations tagged with any specific validity condition.
The Comparand register may be shifted one bit at a time to
the right or left by issuing a Shift Right or Shift Left
instruction, with the right and left limits for the
wrap-around determined by the CAM/RAM partitioning
set in the Control register. During shift rights, bits shifted
off the LSB of the CAM partition reappear at the MSB of
the CAM partition. Likewise, bits shifted off the MSB of
the CAM partition reappear at the LSB during shift lefts.
Status Register
The 32-bit Status register, shown in Status Register Bits on
page 25, is the default source for Command Read cycles.
Bit 31 (internal Full flag) goes LOW if the particular
device has no empty memory locations. Bit 30 is the
internal Multiple Match flag, which goes LOW if a
Multiple match was detected. Bit 29 and Bit 28 are the
Validity bits, which reflect the validity of the last memory
location read. After a reset, the Validity bits read 11 until a
read or move from memory has occurred. The rest of the
Status register down to bit 1 contains the Page address of
the device and the address of the Highest-Priority match.
After a reset or a no-match condition, the match address
bits are all 1s. Bit 0 is the internal Match flag, which goes
LOW if a match was found in this particular device.
Mask Registers (MR1, MR2)
The Mask registers can be used in two different ways:
either to mask compares or to mask data writes and moves.
Either Mask register can be selected in the Control register
to mask every compare, or selected by instructions to
participate in data writes or moves to and from Memory. If
a bit in the selected Mask register is set to a 0, the
corresponding bit in the Comparand register enters into a
masked compare operation. If a Mask bit is a 1, the
corresponding bit in the Comparand register does not enter
into a masked compare operation. Bits set to 0 in the Mask
register cause corresponding bits in the destination register
or memory location to be updated when masking data
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writes or moves, while a bit set to 1 prevents that bit in the
destination from being changed.
Either the Foreground or Background MR1 can be set
active, but after a reset, the Foreground MR1 is active by
default. MR2 incorporates a sliding mask, where the data
can be replicated one bit at a time to the right or left with
no wrap-around by issuing a Shift Right or Shift Left
instruction. The right and left limits are determined by the
CAM/RAM partitioning set in the Control register. For a
Shift Right the upper limit bit is replicated to the next
lower bit, while for a Shift Left the lower limit bit is
replicated to the next higher bit.