mh1020 Music Semiconductors, Inc., mh1020 Datasheet - Page 5

• Manufacturer Part Number: mh1020
• Description: Hla Packaged Asynchronous Data Recognition And Recall Processor
• Manufacturer: Music Semiconductors, Inc.

FUNCTIONAL DESCRIPTION
The MH is a Content Addressable Memory (CAM) with
16-bit I/O for network address filtering and translation,
virtual memory, data compression, caching, and table
lookup applications. The memory consists of static CAM,
organized in 64-bit data fields. Each data field can be
partitioned into a CAM and a RAM subfield on 16-bit
boundaries. The contents of the memory can be randomly
accessed or associatively accessed by the use of a
compare. During automatic comparison cycles, data in the
Comparand register is automatically compared with the
“Valid” entries in the memory array. The Device ID can be
read using a TCO PS instruction (see Persistent Source
Register Bits on page 25).
Data Input and Output Characteristics
The data inputs and outputs of the MH are multiplexed for
data and instructions over a 16-bit I/O bus. Internally, data
is handled on a 64-bit basis, since the Comparand register,
the Mask registers, and each memory entry are 64 bits
wide. Memory entries are globally configurable into CAM
and RAM segments on 16-bit boundaries. Seven different
CAM/RAM splits are possible, with the CAM width going
from one to four segments, and the remaining RAM width
going from three to zero segments. Finer resolution on
compare width is possible by invoking a Mask register
during a compare, which allows global masking on a bit
basis. The CAM subfield contains the associative data,
which enters into compares, while the RAM subfield
contains the associated data, which is not compared. In
LAN bridges, the RAM subfield could hold, for example,
port-address and aging information related to the
destination or source address information held in the CAM
subfield of a given location. In a translation application,
the CAM field could hold the dictionary entries, while the
RAM
instantaneous response.
Validity Bits
Each entry has two validity bits associated with it to define
its particular type: Empty, Valid, Skip, or RAM. When
data is written to the active Comparand register, and the
active Segment Control register reaches its terminal count,
the contents of the Comparand register are automatically
compared with the CAM portion of all the valid entries in
the memory array. For added versatility, the Comparand
register can be barrel-shifted right or left one bit at a time.
A Compare instruction then can be used to force another
compare between the Comparand register and the CAM
portion of memory entries of any one of the four validity
types. After a Read or Move from Memory operation, the
validity bits of the location read or moved are copied into
the Status register, where they can be read using
Command Read cycles.
Rev. 1
field
holds
the
translations,
with
almost
5
Data Movement (Read/Write)
Data can be moved from one of the data registers (CR,
MR1, or MR2) to a memory location that is based on the
results of the last comparison (Highest-Priority Match or
Next Free), or to an absolute address, or to the location
pointed to by the active Address register. Data can also be
written directly to the memory from the DQ bus using any
of the above addressing modes. The Address register may
be directly loaded and may be set to increment or
decrement, allowing DMA-type reading or writing from
memory.
Configuration Register Sets
Two sets of configuration registers (Control, Segment
Control, Address, Mask Register 1, and Persistent Source
and Destination) are provided to permit rapid context
switching between foreground and background activities.
The currently active set of configuration registers controls
writes, reads, moves, and compares. The foreground set
typically would be pre-loaded with values useful for
comparing input data, often called filtering, while the
background set would be pre-loaded with values useful for
housekeeping activities such as purging old entries.
Moving from the foreground task of filtering to the
background task of purging can be done by issuing a
single instruction to change the current set of
configuration registers. The match condition of the device
is reset whenever the active register set is changed.
Control Register
The active Control register determines the operating
conditions within the device. Conditions set by this
register’s contents are reset, enable or disable Match flag,
enable or disable Full flag, CAM/RAM partitioning,
disable or select masking conditions, disable or select
auto-incrementing or auto-decrementing the Address
register, and select Standard or Enhanced mode. The
active Segment Control register contains separate counters
to control the writing of 16-bit data segments to the
selected persistent destination, and to control the reading
of 16-bit data segments from the selected persistent
source.