emc2106 Standard Microsystems Corp., emc2106 Datasheet - Page 72

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emc2106

Manufacturer Part Number
emc2106
Description
Emc2106 Dual Rpm-based Linear Fan Controller With Hardware Thermal Shutdown
Manufacturer
Standard Microsystems Corp.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
emc2106-DZK-TR
Manufacturer:
SMSC
Quantity:
20 000
ADDR
43h
83h
Revision 1.74 (05-08-08)
6.26
R/W
R/W
R/W
2
0
0
0
0
1
1
1
1
Configuration
Configuration
REGISTER
The Fan Configuration 2 Register controls the tachometer measurement and advanced features of the
RPM based Fan Speed Control Algorithm.
Bit 6 - EN_RRCx - Enables ramp rate control when the corresponding fan driver is operated in the
Direct Setting Mode or the Direct Setting with LUT mode.
Bit 5 - GLITCH_ENx - Disables the low pass glitch filter that removes high frequency noise injected
on the TACHx pin. If the LOWDRIVE bit is set, this bit is ignored and the filter is automatically disabled.
Bits 4 - 3 - DER_OPTx[1:0] - Control some of the advanced options that affect the derivative portion
of the RPM based Fan Speed Control Algorithm as shown in
Fan Configuration 2 Registers
Fan 1
Fan 2
‘0’ (default) - Ramp rate control is disabled. When the fan driver is operating in Direct Setting mode
or Direct Setting with LUT mode, the fan setting will instantly transition to the next programmed
setting.
‘1’ - Ramp rate control is enabled. When the fan driver is operating in Direct Setting mode or Direct
Setting with LUT mode, the fan drive setting will follow the ramp rate controls as determined by the
Fan Step and Update Time settings. The maximum fan drive setting step is capped at the Fan Step
setting and is updated based on the Update Time as given by
‘0’ - The glitch filter is disabled.
‘1’ (default) - The glitch filter is enabled.
2
2
UPDATE[2:0]
B7
-
-
1
0
0
1
1
0
0
1
1
Table 6.35 Fan Configuration 1 Registers
RRC1
RRC2
EN_
EN_
B6
Table 6.34 Update Time
DATASHEET
Dual RPM-Based Linear Fan Controller with Hardware Thermal Shutdown
GLITCH
GLITCH
_EN1
_EN2
B5
72
0
0
1
0
1
0
1
0
1
DER_OPT1 [1:0]
DER_OPT2 [1:0]
B4
B3
Table
Table
6.36.
ERR_RNG[1:0]
ERR_RNG[1:0]
400ms (default)
B2
UPDATE TIME
6.34.
1200ms
1600ms
100ms
200ms
300ms
500ms
800ms
B1
SMSC EMC2106
LOWD
LOWD
RIVE1
RIVE2
Datasheet
B0
DEFAULT
38h
38h

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