hi-3111pstf Holt Integrated Circuits, Inc., hi-3111pstf Datasheet
hi-3111pstf
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hi-3111pstf Summary of contents
Page 1
... The HI-3112 provides an option of a CLKOUT pin instead of a SPLIT pin, which may be used as the main system clock clock input for other devices in the system. Finally, the HI-3113 provides all options (both CLKOUT and SPLIT pins very compact QFN-44 package ...
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... CLKOUT OUT (see ordering information) PRIMARY FUNCTIONS OF HI-3110 LOGIC BLOCKS SPI PROTOCOL BLOCK Handles data transfers between the host and the chip REGISTERS BLOCK Stores configuration data BIT TIMING BLOCK Sets the data strobe and bit period TRANSMIT BLOCK Manages transmission protocol ...
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... Active high. Transmit Enable pin. When the TXEN pin is asserted, any message in the Transmit FIFO will be automatically loaded to the Transmit buffer and sent if the bus is available. This pin is logically ORed with the TXEN and TX1M bits in the CTRL1 register. When the TXEN pin is reset, messages loaded to the FIFO will not be sent until TXEN or TX1M bits are set in the CTRL1 register ...
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... In addition, the Interrupt Flag Register, INTF, monitors 8 operational conditions, any or all of which may be directed to the INT pin by enabling bits in the Interrupt Enable Register, INTE. Similarly, the Status Flag Register, STATF, bits reflect the status of selected FIFO and Error properties ...
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... Monitor mode is activated by programming the MODE<2:0> bits to <010> in the CTRL0 register. SLEEP MODE The HI-3110 can be placed in a low power sleep mode if there is no bus activity and the transmit FIFO is empty. In this mode, the internal oscillator and all analog circuitry (transceiver) are off, drawing typically less than 20 A ...
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... I Intermission and Bus-Idle. The Intermission consists of three recessive bits, however the following notes apply: a) detection of a dominant bit on the bus at the third slot is interpreted as a SOF, b) detection of a dominant bit in either the first or second slots results in generation of an overload frame (see below). ...
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... Passive Error Flag: A passive error flag consists of 6 recessive bits. This is followed by the 8 recessive bits of the error delimiter. Therefore, an error frame sent by an error- passive node consists of 14 consecutive recessive bits. Since this will not disturb the bus, a transmitting node will continue to transmit unless it detects the error itself, or another error-active node detects the error ...
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... Standard Data Frame HI-3110 SOF or Idle Bus Intermission Del ACK bit Slot ACK KEY. Del CRC SOF IDxx RTR IDE r0 DLCx CRC Del ACK Slot bit ACK Del EOF IFS DLC0 DLC3 r0 bit Reserved IDE RTR ID18 ID23 ID28 SOF Figure 2. Standard Frame Format. ...
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... Extended Data Frame HI-3110 SOF or Idle Bus Intermission Del ACK bit Slot ACK Del CRC KEY. SOF IDxx SRR IDE RTR r1 r0 DLCx CRC Del ACK Slot bit ACK Del EOF IFS DLC0 DLC3 r0 bits Reserved r1 RTR ID0 ID9 ID17 IDE ...
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... Remote Frame Figure 4. Remote Frame Format (Extended Identifier). HI-3110 SOF or Idle Bus Intermission Del ACK bit Slot ACK Del CRC DLC0 DLC3 r0 bits Reserved r1 RTR ID0 ID9 ID17 IDE SRR ID18 ID23 ID28 SOF HOLT INTEGRATED CIRCUITS 10 ...
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... Error Frame HI-3110 Intermission DLC0 DLC3 r0 bits Reserved r1 RTR ID0 ID9 ID17 IDE SRR ID18 ID23 ID28 SOF Figure 5. Error Frame Format. HOLT INTEGRATED CIRCUITS 11 ...
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... Overload Frame HI-3110 Intermission Illegal Dominant Bit in IFS Figure 6. Overload Frame Format HOLT INTEGRATED CIRCUITS 12 ...
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... It will then wait for the next bus idle state and attempt to re- transmit. Eventually, lower priority messages will gain access to the bus. Figure 7 shows an example of how this works for a frame with a standard identifier. Standard ID Arbitration Field 1 ...
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... Seg), phase buffer segment 1 (Phase Seg1) and phase buffer segment 2 (Phase Seg2). This is illustrated in figure 8. The HI-3110 fixes the Sync Seg at 1Tq. Prop Seg and Phase Seg1 are treated as one time segment, TSeg1, which is programmable from 2Tq to 16Tq. ...
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... Sample Point The sample point is the point in the bit time at which the bit logic level is interpreted located at the end of Phase Seg1. The HI-3110 also allows three sample points to be taken. In this case, two other sample points are taken prior to the end of Phase Seg1 (at one-half TQ intervals) and the value of the bit is determined by a majority decision ...
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... REGISTERS This section describes the HI-3110 registers. All register bits are active high. Unless otherwise indicated, all registers are reset in software to the logic zero condition after Master Reset. For all registers, bit 7 is the most significant: REGISTER R/W CTRL0 R/W CTRL1 R/W BTR0 R/W BTR1 ...
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... When this bit is set, the HI-3110 will automatically wake up from Sleep Mode to Monitor Mode when it detects activity on the bus. 3 RESET R/W 0 Setting this bit causes HI-3110 reset to occur. The bit should then be cleared by writing a logic “0” following reset. A reset may also be performed by setting the MR pin or issuing the “MR” SPI command, 0x56. 2 BOR R/W 0 Bus-off Reset ...
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... FILTON = 0, meaning filtering is turned off and every valid CAN message is accepted into the receive FIFO. acceptance filters and masks. 3 OSCOFF R/W 0 Oscillator off. This bit should be set to a one if an external clock is used. In this case the external clock is connected to the OSCIN pin and OSCOUT should be left floating. 2 Not used R/W 0 1-0 CLKDIV1:0 ...
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... SPI Op-code 0x18) (Read, SPI Op-code 0xD6) BTR0 defines the value of the Re-synchronization Jump Width (SJW) and the Baud Rate Prescaler (BRP). This register can be read anytime and written only in init mode (MODE<2:0> bits set to <1xx> in the CTRL0 register). Bit Name ...
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... SPI Op-code 0x1A) (Read, SPI Op-code 0xD8) BTR1 configures the CAN protocol bit timing segments in terms of time quanta (Tq) and sets the number of sampling points. This register can be read anytime and written only in init mode (MODE<2:0> bits set to <1xx> in the CTRL0 register). ...
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... TRANSMIT ERROR COUNTER REGISTER: TEC (Write, SPI Op-code 0x26) (Read, SPI Op-code 0xEC) The TEC register reflects the current value of the CAN Transmit Error Counter. This register can be written by SPI command for test purposes. Bit Name R/W Default Description 7-0 TEC7:0 R/W 0x00 Transmit Error Counter bits <7:0>. ...
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... MESSAGE STATUS REGISTER: MESSTAT (Read only) (Read, SPI Op-code 0xDA) This register reflects transmission status and also which filters were responsible for filtering valid received messages read-only. Bit Name R/W Default Description 7-4 FILHIT3 Filter hit bits <3:0>. These bit combinations indicate which filters were responsible for filtering received messages ...
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... Default Description 7 BUSOFF R 0 Bus-off status indicator. This bit is set when TEC > 255. Node is in bus off condition. The bit is reset by HI-3110 when a successful bus recovery sequence is detected (128 x 11 consecutive recessive bits). d the FILHIT3:0 bits will reflect this value. 6 TXERRP R 0 Transmit Error Passive status indicator ...
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... Interrupt Enable Register INTE are set, the INT pin will be latched high when any of the corresponding INTF bits are set. This alerts the host that one of the conditions below has occurred. Reading this register will clear all bits and reset the INT pin. ...
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... SPI Op-code 0x1C) (Read, SPI Op-code 0xE4) Setting bits in the Interrupt Enable Register causes a hardware interrupt to be generated at the INT pin when the corresponding bits in the Interrupt Flag Register are set by HI-3110 as a result of the related events described below. Bit Name R/W ...
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... TXMTY is set and a message is loaded to the transmit FIFO, TXMTY will be automatically cleared by HI-3110). If individual bits in the Status Flag Enable Register STATFE are set, the STAT pin will pulse high when any of the enabled STATF bits are set. The value of individual bits in the STATF register may also be reflected on the GP1 and GP2 pins by setting the correct bit combinations in the General Purpose Pins Enable Register GPINE ...
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... SPI Po-code 0x1E) (Read, SPI Op-code 0xE6) Setting bits in the Status Flag Enable Register causes the STAT pin to go high when any of the corresponding bits in the Status Flag Register are set by HI-3110 as a result of the related events described below. Bit Name ...
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... GP1 pin is asserted when ERRP bit is set in register STATF. 1100: GP1 pin is asserted when ERRW bit is set in register STATF. 1101: GP1 pin is asserted when TXHISF bit is set in register STATF. 1110: GP1 pin is asserted when TXFULL bit is set in register STATF. 1111: GP1 pin is asserted when TXMPTY bit is set in register STATF. ...
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... SPI Op-code 0xFA) Bit Name R/W Default Description 7-0 T7:0 R/W 0x00 Free Running Timer Lower Byte, bits <7:0>. HI-3110 T15 LSB MSB The timer is clocked by the HI-3110 bit clock and continuously T7 LSB MSB HOLT INTEGRATED CIRCUITS 29 0 Note: A timer overrun is not 0 ...
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... CPHA (clock phase). The possible CPHA combinations define four possible "SPI Modes". Without describing details of the SPI modes, the HI-3110 operates in mode 0 where input data for each device (master and slave) is clocked on the rising edge of SCK, and output data for each device changes on the falling edge (CPHA = 0, CPOL = 0) ...
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... HOST SERIAL PERIPHERAL INTERFACE, cont. HI-3110 SPI COMMANDS For the HI-3110, each SPI read or write operation begins with an 8-bit command byte transferred from the host to the device after assertion Since HI-3110 command byte reception is half-duplex, the host discards the dummy byte it receives while serially transmitting the command byte ...
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... Read Bit Timing Register 1 Read Message Status Register Read Error Register Read Interrupt Flag Register Read Status Flag Register Read Interrupt Enable Register Read Status Flag Enable Register HOLT INTEGRATED CIRCUITS HI-3110 Command Data Field Hex 0x42 15 bytes 0x44 13 bytes 0x46 ...
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... Table 1. SPI Instruction Set (cont.) SPI Instruction READ Commands (ctd) Read General Purpose Pins Enable Register Read REC Register Read TEC Register Read Transmit History FIFO Reserved (Factory test purposes only) Reserved (Factory test purposes only) Reserved (Factory test purposes only) ...
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... Write Mask 2 ID Write Mask 3 ID Write Mask 4 ID Write Mask 5 ID Write Mask 6 ID Write Mask 7 ID HOLT INTEGRATED CIRCUITS HI-3110 Command Data Field Hex 0x12 bytes) for Std frame bytes) for Ext frame (N = number of loaded messages ...
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... TXEN bit in CTRL1 (or pulling TXEN pin low). In this case, the current message will be completed and any remaining messages in the transmit FIFO will not be transmitted. ...
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... HI-3110 Transmit Message Flow Diagram HI-3110 HOLT INTEGRATED CIRCUITS 36 ...
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... Data Byte 8 * Note: The Message Tag is a host-assigned identifier that is stored along with a time tag in the Transmit History FIFO. It can be used by the host to log successfully transmitted messages at a later time. HI-3110 Table 2. SPI Transmit Data Format Bit Description (”x” = Don’t care) ...
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... Data Byte 8 * Note: The Message Tag is a host-assigned identifier that is stored along with a time tag in the Transmit History FIFO. It can be used by the host to log successfully transmitted messages at a later time. HI-3110 Table 2. SPI Transmit Data Format Bit Description (”x” = Don’t care ...
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... ID for acceptance to occur mask ID bit is logic zero, then acceptance will occur regardless of the value of the CAN ID bit. In this case, the filter bits are don’t care. Following reset, all eight filter and mask registers should be loaded before enabling the FILTON bit. ...
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... Match ? No ID Acceptance Filter 1 ID Mask Filter 1 Yes Match ? No ID Acceptance Filter 7 ID Mask Filter 7 Yes Match ? No Message not stored Figure 13. Receive Buffer Structure HOLT INTEGRATED CIRCUITS HI-3110 MESSTAT Register FILHIT3:0 bits FILHIT3:0 = 1000 FILHIT3:0 = 1001 FILHIT3:0 = 1111 40 Load Receive FIFO ...
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... Standard ID) 3 ID14 to ID7 (Note: Written as zeros for Standard ID) 4 ID6 to ID0 (Note: Written as zeros for Standard ID) 5 Data Byte 1 6 Data Byte 2 HI-3110 Bit Description (”x” = Don’t care) Bit Description (”x” = Don’t care) HOLT INTEGRATED CIRCUITS ...
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... Temporary Receive Buffer) 2 Time Tag Upper Byte (Note: This byte only applies to time tag SPI instructions; see Table 1) 3 Time Tag Lower Byte (Note: This byte only applies to time tag SPI instructions; see Table 1) 4 ID28 to ID21 5 ID20 to ID18, SRR, IDE, ID17 to ID15 ...
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... TIMING DIAGRAMS CS t CHH SCK SCKH SCKL SCK SO Hi Impedance HI-3110 SERIAL INPUT TIMING DIAGRAM t CSS t t SCKR DH MSB SERIAL OUTPUT TIMING DIAGRAM t DV MSB HOLT INTEGRATED CIRCUITS 43 t CPH t t SCKF CSH LSB t CPH t CHZ LSB Hi Impedance ...
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... fixed thermal resistance value which depends on the package and circuit board mounting conditions Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
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... High-Level Output Voltage Low-Level Output Voltage Output sink current Output source current Bus Lines (pins CANH, CANL) CANH dominant output voltage CANL dominant output voltage Matching of dominant output voltage, VCC − VCANH − VCANL Dominant differential output voltage Recessive differential output voltage ...
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... SCK falling edge CS inactive between SPI instructions SPI SI Data set-up time to SCK rising edge SPI SI Data hold time after SCK rising edge SO high-impedance after SCK falling edge CAN Bus Data Rate Time Out HI-3110 SYMBOL SCK clock frequency ...
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... HI-3110 Internal transceiver O(CANL) Dominant Recessive Figure 14. CAN Bus Driver Circuit Internal W 300 CANH transceiver DIFF(d)(o) L CANL W 300 Figure 15. CAN Bus Driver (Dominant) Test Circuit Internal CANH transceiver 0V CANL Figure 16. CAN Bus Driver Short-Circuit Test HOLT INTEGRATED CIRCUITS 47 V DIFF(d)(o) ...
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... Figure 17. Split-Termination Connection CANH V DIFF(d)( DIFF(d)(i) I(CANH) I(CANL) CANL V I(CANL) Figure 18. CAN Bus Receiver Common Mode Voltage Test OSCIN HI-3110 OSCOUT 1 10pF typ. Figure 19. Suggested Crystal Oscillator Circuit HOLT INTEGRATED CIRCUITS Internal Transceiver RXD C1 Crystal R Resonator ...
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... OSCI 3 GP1 3113PCx GP2 6 TXEN 7 CLKOUT Pin Plastic QFN, 7mm x 7mm HI-3110 18 INT VLOGIC OSCOUT OSCIN GP1 GP2 5 13 SCK TXEN 6 12 STAT CLKOUT 7 11 TXD GND CANL 9 18-Pin Plastic SOIC - WB Package ...
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... TO +85°C T -55°C TO +125°C PACKAGE DESCRIPTION PS 18 PIN PLASTIC WIDE BODY SOIC (18HW PIN PLASTIC QFN (44PCS) (HI-3113 only) DESCRIPTION 3110 Integrated transceiver with SPLIT pin option Digital-only option, no transceiver 3111 Integrated transceiver with CLKOUT pin option 3112 Integrated transceiver with both SPLIT & ...
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... PLASTIC SMALL OUTLINE (SOIC (Wide Body) (11.531 ± .20) .4065 ± .0125 (10.325 ± .32) .050 BSC (1.27) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) 44-PIN PLASTIC CHIP-SCALE PACKAGE .276 BSC (7.00) .276 Top View BSC (7.00) .039 max (1.00) BSC = “ ...