hi-3111pstf Holt Integrated Circuits, Inc., hi-3111pstf Datasheet - Page 25

• Manufacturer Part Number: hi-3111pstf
• Description: Avionics Can Controller With Integrated Transceiver
• Manufacturer: Holt Integrated Circuits, Inc.

Setting bits in the Interrupt Enable Register causes a hardware interrupt to be generated at the INT pin when the
corresponding bits in the Interrupt Flag Register are set by HI-3110 as a result of the related events described below.
Bit Name
7
6
5
4
3
2
1
0
INTERRUPT ENABLE REGISTER: INTE
(Write SPI Op-code 0x1C)
(Read, SPI Op-code 0xE4)
RXTMPIE
RXFIFOIE
TXCPLTIE
BUSERRIE
MCHGIE
WAKEUPIE
F1MESSIE
F0MESSIE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default Description
0
0
0
0
0
0
0
0
Enable interrupt when a message is received in the temporary receive buffer (unfiltered).
Setting this bit causes a hardware interrupt to be generated at the INT pin when the RXTMP bit
is set in the INTF register.
Enable interrupt when a message is received in the receive FIFO (filtered).
Setting this bit causes a hardware interrupt to be generated at the INT pin when the
RXFIFO bit is set in the INTF register.
Enable interrupt when a successful transmission is complete.
Setting this bit causes a hardware interrupt to be generated at the INT pin when the TXCPLT bit
is set in the INTF register.
Enable interrupt when a bus error occurs.
Setting this bit causes a hardware interrupt to be generated at the INT pin when the BUSERR
bit is set in the INTF register.
Enable interrupt when a mode change occurs.
Setting this bit causes a hardware interrupt to be generated at the INT pin when the MCHG bit
is set in the INTF register.
Enable interrupt when HI-3110 wakes up from Sleep Mode.
Setting this bit causes a hardware interrupt to be generated at the INT pin when the WAKEUP
bit is set in the INTF register.
Enable interrupt when filter one passes a message.
Setting this bit causes a hardware interrupt to be generated at the INT pin when the F1MESS
bit is set in the INTF register.
Enable interrupt when filter zero passes a message.
Setting this bit causes a hardware interrupt to be generated at the INT pin when the F0MESS
bit is set in the INTF register.
HOLT INTEGRATED CIRCUITS
HI-3110
MSB
7
25
6
5
4
3
2
1
LSB
0