hi-3111pstf Holt Integrated Circuits, Inc., hi-3111pstf Datasheet - Page 26

• Manufacturer Part Number: hi-3111pstf
• Description: Avionics Can Controller With Integrated Transceiver
• Manufacturer: Holt Integrated Circuits, Inc.

The Status Flag Register STATF bits will be set by HI-3110 when the corresponding related events described below occur. Unlike the
Interrupt Flag Register, reading this register will NOT clear all bits. These bits are reset automatically by HI-3110 when the described
status for each bit changes (e.g. if TXMTY is set and a message is loaded to the transmit FIFO, TXMTY will be automatically cleared
by HI-3110). If individual bits in the Status Flag Enable Register STATFE are set, the STAT pin will pulse high when any of the enabled
STATF bits are set. The value of individual bits in the STATF register may also be reflected on the GP1 and GP2 pins by setting the
correct bit combinations in the General Purpose Pins Enable Register GPINE.
Bit Name
7
6
5
4
3
2
1
0
STATUS FLAG REGISTER: STATF
(Read-only)
(Read, SPI Op-code 0xE2)
TXMTY
TXFULL
TXHISF
ERRW
ERRP
BUSOFF
RXFMTY
RXFFULL
R/W
R
R
R
R
R
R
R
R
Default Description
1
0
0
0
0
0
1
0
Transmit FIFO is empty.
This bit is set when the transmit FIFO is empty. This is the default following Reset.
Transmit FIFO is full.
This bit is set when the transmit FIFO is full.
Transmit history FIFO full.
This bit is set when the transmit history FIFO is full. Up to eight messages can be stored in the
transmit history FIFO (Note: a user generated message tag and a time tag are stored with each
message).
Error warning flag.
This bit is set when 96
Error passive indicator.
This bit is set when the device enters error passive mode.
BUSOFF indicator.
This bit is set when the device enters bus-off state.
Receive FIFO empty.
This bit is set when the receive FIFO is empty. This is the default following Reset.
Receive FIFO full.
This bit is set when the receive FIFO is full.
HOLT INTEGRATED CIRCUITS
£
HI-3110
MSB
(TEC or REC)
7
26
6
5
4
£
3
127.
2
1
LSB
0