am49lv6408m Meet Spansion Inc., am49lv6408m Datasheet - Page 14

• Manufacturer Part Number: am49lv6408m
• Description: Stacked Multi-chip Mcp 64 Mbit 4 M ? 16 Bit Flash Memory And 8 Mbit 512k ? 16 Bit Pseudo Static Ram
• Manufacturer: Meet Spansion Inc.

V
but the standby current will be greater. The device re-
quires standard access time (t
when the device is in either of these standby modes,
before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
Refer to the
current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
this mode when addresses remain stable for t
30 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data is latched and always available to the system.
Refer to the
sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
12
CC
± 0.3 V, the device will be in the standby mode,
Sector
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
DC Characteristics
DC Characteristics
Table 2. Am29LV640MT Top Boot Sector Architecture
Sector Address
0000000xxx
0000001xxx
0000010xxx
0000011xxx
0000100xxx
0000101xxx
0000110xxx
0000111xxx
0001000xxx
0001001xxx
0001010xxx
0001011xxx
0001100xxx
0001101xxx
0001101xxx
0001111xxx
0010000xxx
0010001xxx
0010010xxx
0010011xxx
0010100xxx
0010101xxx
0010110xxx
0010111xxx
0011000xxx
A21–A12
table for the automatic
A D V A N C E
table for the standby
CE
) for read access
ACC
Am49LV6408M
+
I N F O R M A T I O N
Sector Size
(Kwords)
SET# pin is driven low for at least a period of t
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
draws CMOS standby current (I
at V
be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
Refer to the
rameters and to Figure 16 for the timing diagram.
Output Disable Mode
When the OE# input is at V
disabled. The output pins are placed in the high
impedance state.
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
IL
but not within V
AC Characteristics
SS
±0.3 V, the standby current will
A0000h–A7FFFh
A8000h–AFFFFh
B0000h–B7FFFh
B8000h–BFFFFh
C0000h–C7FFFh
IH
08000h–0FFFFh
18000h–1FFFFh
28000h–2FFFFh
38000h–3FFFFh
48000h–4FFFFh
58000h–5FFFFh
68000h–6FFFFh
78000h–7FFFFh
88000h–8FFFFh
98000h–9FFFFh
Address Range
00000h–07FFFh
10000h–17FFFh
20000h–27FFFh
30000h–37FFFh
40000h–47FFFh
50000h–57FFFh
60000h–67FFFh
70000h–77FFFh
80000h–87FFFh
90000h–97FFFh
, output from the device is
CC4
tables for RESET# pa-
(x16)
SS
). If RESET# is held
November 5, 2003
±0.3 V, the device
RP
, the