lrs1383 Sharp Microelectronics of the Americas, lrs1383 Datasheet - Page 105

• Manufacturer Part Number: lrs1383
• Description: Stacked Chip 32m Flash And 8m Sram
• Manufacturer: Sharp Microelectronics of the Americas

5.2 Software Design Considerations
5.2.1 WSM (Write State Machine) Polling
The status register bit SR.7 provides a software method of
detecting block erase, full chip erase, (page buffer)
program and OTP program completion. After the Block
Erase, Full Chip Erase, (Page Buffer) Program or OTP
Program command is written to the CUI (Command User
Interface), SR.7 goes to "0". It will return to "1" when the
WSM (Write State Machine) has completed the internal
algorithm.
The status register bit SR.7 is "1" state when the device is
in the following mode.
5.2.2 Attention to Program Operation
Do not re-program "0" data for the bit in which "0" has
been already programmed. This re-program operation
may generate the bit which cannot be erased.
To change the data from "1" to "0", take the following
steps.
For example, changing the data from "10111101" to
"10111100" requires "11111110" programmed.
• The device can accept the next command.
• Block erase is suspended and (page buffer) program
• (Page buffer) program is suspended.
• Reset mode
• Program "0" for the bit in which you want to change
• Program "1" for the bit in which "0" has been already
operation is not executed.
the data from "1" to "0".
programmed.
(When "1" is programmed, erase/program operations
are not executed onto the memory cell in flash
memory.)
Appendix to Spec No.: MFM2-J13207
FUM00701
Model No.: LRS1383
5.3 Data Protection Method
Noises having a level exceeding the limit specified in the
specification may be generated under specific operating
conditions on some systems. Such noises, when induced
onto WE# signal or power supply, may be interpreted as
false commands and causes undesired memory updating.
To protect the data stored in the flash memory against
unwanted writing, systems operating with the flash
memory should have the following write protect designs,
as appropriate:
1) Protection of data in each block
2) Protection of data with V
3) Protection of data with RST#
To prevent the recognition of false commands as write
commands, system designer should consider the method
for reducing noises on WE# signal.
• ny locked block by setting its block lock bit is
• For detailed block locking scheme, refer to Sections
• When the level of V
• Especially during power transitions such as power-up
• For detailed description on RST# control, refer to
The below describes data protection method.
Protection against noises on WE# signal
protected against the data alternation. When WP# is
V
down bit is protected from lock status changes.
By using this function, areas can be defined, for
example, program area (locked blocks), and data area
(unlocked blocks).
4.12 to 4.14.
lockout voltage), write functions to all blocks
including OTP block are disabled. All blocks are
locked and the data in the blocks are completely
protected.
and power-down, the flash memory enters reset mode
by bringing RST# to V
operation to all blocks including OTP block.
Section 5.1.5.
IL
, any locked-down block by setting its block lock-
March 1, 2001
PP
IL
is lower than V
PP
, which inhibits write
control
PPLK
Rev. 2.20
(V
PP
59