lrs1383 Sharp Microelectronics of the Americas, lrs1383 Datasheet - Page 77

• Manufacturer Part Number: lrs1383
• Description: Stacked Chip 32m Flash And 8m Sram
• Manufacturer: Sharp Microelectronics of the Americas

4.8 Program Command
A two-cycle command sequence written to the target
partition initiates a word program operation. Read
operations to the target partition to be programmed output
the status register data until another valid command is
written. At the first cycle, write command (standard 40H
or alternate 10H) and an address of memory location to be
programmed, followed by the second write that specifies
the address and data. The WSM then takes over,
controlling the internal word program algorithm. The
system CPU can detect the word program completion by
analyzing the output data of the status register bit SR.7.
Figure 7.1 and Figure 7.2 show a program flowchart.
The internal WSM verify only detects errors for "1"s that
are not successfully programmed to "0"s. Check the status
register bit SR.4 at the end of word program. If a word
program error is detected, the status register should be
cleared before system software attempts corrective
actions. The partition remains in read status register mode
until it receives another command.
For reliable word program operation, apply the specified
voltage on V
voltage, word program operations are not guaranteed. For
example, attempting a word program at V
causes SR.4 and SR.3 being set to "1". Also, successful
word program requires for the selected block is unlocked.
When word program is attempted to the locked block, bits
SR.4 and SR.1 will be set to "1".
Word program operation may occur in only one partition
at a time. Other partitions must be in one of the read
modes.
CC
and V
PPH1/2
on V
Appendix to Spec No.: MFM2-J13207
PP
. In the absence of this
PP
V
PPLK
FUM00701
Model No.: LRS1383
4.9 Page Buffer Program Command
The LH28F320BX/LH28F640BX series has two planes
of 16-word page buffer, which can perform fast sequential
programming up to 32 words. The data are once loaded to
the page buffer and programmed to the flash array when
the confirm command (D0H) is written. See the flowchart
in Figure 8.1 and Figure 8.2.
The page buffer program is executed by at least four-
cycle or up to 19-cycle command sequence. First, write
the Page Buffer Program setup command (E8H) and start
address to the partition’s CUI. At this point, read
operations to the target partition to be programmed output
the extended status register data (see Table 10). Check the
extended status register data. If the extended status
register bit XSR 7 is "0", no page buffer is available and
Page Buffer Program setup command which has just been
written is ignored. To retry, continue monitoring XSR.7
by writing Page Buffer Program setup (E8H) with
program address until XSR.7 transitions to "1". When
XSR.7 transitions to "1", the setup command written is
valid. Then, at the second cycle, write the word count
[N]-1 and start address if the number of words to be
programmed is [N] in total. That is, when the number of
[N] is 1 word, write (00H); if [N] is 16 words, write
(0FH). The word count [N]-1 must be less than or equal to
0FH. Attempting to write more than 0FH for the word
count causes the sequence error and the status register bits
SR.5 and SR.4 are set to "1". After writing a word count
[N]-1, read operations to the target partition to be
programmed output the status register data. At the third
cycle following the write of [N]-1, write the first data to
be programmed and start address to the partition’s CUI.
Lower 4 bits (A
to the page buffer address and the data are stored in the
page buffer. At the fourth and subsequent cycles, write
additional data and address, depending on the count. All
subsequent address must lie within the start address plus
the count. After writing the Nth word data, write the
confirm command (D0H) and an address within the target
partition at the last cycle. This initiates the WSM to being
transferring the data from the page buffer to the flash
array. If a command other than the confirm command
(D0H) is written, sequence error occurs and status register
bits SR.5 and SR.4 of the partition are set to "1". When
the data are transferred from the page buffer to the flash
array, the status register bit SR.7 is set to "0". Then, the
target partition is in the page buffer program busy mode.
0
March 1, 2001
-A
3
) of the start address also correspond
Rev. 2.20
31