lrs1383 Sharp Microelectronics of the Americas, lrs1383 Datasheet - Page 52

• Manufacturer Part Number: lrs1383
• Description: Stacked Chip 32m Flash And 8m Sram
• Manufacturer: Sharp Microelectronics of the Americas

DQ
Symbol
A
A
WAIT#
ADV#
RST#
CLK
WE#
WP#
CE#
OE#
0
0
0
-A
-A
-DQ
20
21
15
OUTPUT
OUTPUT
INPUT/
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
Type
Synchronous burst mode will be available for future device.
Appendix to Spec No.: MFM2-J13207
ADDRESS INPUTS: Inputs for addresses. 32M: A
ADDRESS INPUTS: Inputs for addresses. 64M: A
DATA INPUT/OUTPUTS: Inputs data and commands during CUI (Command User
Interface) write cycles, outputs data during memory array, status register, query,
identifier code and device configuration code reads. Data pins float to high-impedance
(High Z) when the chip or outputs are deselected. Data is internally latched during an
erase or program cycle.
Chip Enable: Activates the device’s control logic, input buffers, decoders and sense
amplifiers. CE#-high (V
standby levels.
CLOCK: Synchronizes the memory to the system bus operating frequency in
synchronous burst mode. The first rising (or falling if RCR.6 is "0") edge latches the
address when ADV# is V
synchronous burst mode.
ADDRESS VALID: Addresses are input to the memory when ADV# is low (V
Addresses are latched on ADV#’s rising edge during read and write operations.
RESET: When low (V
which provides data protection. RST#-high (V
power-up or reset mode, the device is automatically set to asynchronous read array
mode. RST# must be low during power-up.
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of CE# or WE# (whichever goes high first).
WRITE PROTECT: When WP# is V
or program operation can be executed to the blocks which are not locked and locked-
down. When WP# is V
WAIT: Outputs data valid status in synchronous burst mode while OE# is asserted.
When high (V
data. WAIT# is pulled high (V
multiple devices can be tied together to drive one system WAIT# signal. WAIT# is used
only for synchronous burst mode. It also works during a continuous burst mode or 4-, 8-
word burst with no-wrap (RCR.3="1") mode
Table 3.1. Pin Descriptions
OH
) during a burst mode, data is valid. WAIT# low (V
FUM00701
IL
IH
), RST# resets internal automation and inhibits write operations
, lock-down is disabled.
IH
) deselects the device and reduces power consumption to
Model No.: LRS1383
IL
or upon a rising ADV# edge. This is used only for
OH
Name and Function
) by an internal resister. The WAIT# signals of the
IL
, locked-down blocks cannot be unlocked. Erase
March 1, 2001
IH
0
0
-A
-A
) enables normal operation. After
20
21
OL
) indicates invalid
Rev. 2.20
6
IL
).