k4d263238a-gc50 Samsung Semiconductor, Inc., k4d263238a-gc50 Datasheet - Page 13

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k4d263238a-gc50

Manufacturer Part Number
k4d263238a-gc50
Description
1m X 32bit X 4 Banks Double Data Rate Synchronous Ram With Bi-directional Data Strobe And Dll
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
K4D26323RA-GC
AC OPERATING TEST CONDITIONS
CAPACITANCE
Recommended decoupling capacitance added to power line at board.
Note :
DECOUPLING CAPACITANCE GUIDE LINE
Decoupling Capacitance between V
Decoupling Capacitance between V
Input reference voltage for CK(for single ended)
CK and CK signal maximum peak swing
CK signal minimum slew rate
Input Levels(V
Input timing measurement reference level
Output timing measurement reference level
Output load condition
Input capacitance( CK, CK )
Input capacitance(A
Input capacitance
( CKE, CS, RAS,CAS, WE )
Data & DQS input/output capacitance(DQ
Input capacitance(DM0 ~ DM3)
1. V
2. V
All V
All V
DD
SS
Parameter
and V
and V
DD
SS
pins are connected in chip. All V
pins are connected in chip. All V
IH
SSQ
DDQ
/V
0
Parameter
IL
~A
pins are separated each other
Parameter
pins are separated each other.
)
(V
11
DD
, BA
Output
=2.5V, T
0
~BA
DD
DDQ
1
)
and V
A
and V
= 25qC, f=1MHz)
0
~DQ
SS
* VDD / VDDQ=2.8V *
SSQ
SSQ
DDQ
31
)
pins are connected in chip.
pins are connected in chip.
(Fig. 1) Output Load Circuit
(V
Z0=50:
DD
- 13 -
=2.8Vr5%, T
Symbol
C
LOAD
C
C
C
C
C
OUT
IN1
IN2
IN3
IN4
V
=30pF
REF
Symbol
C
C
0.50*V
See Fig.1
DC1
DC2
+0.4/V
Value
V
A
V
1.5
1.0
V
= 0 to 65qC)
REF
tt
tt
=0.5*V
DDQ
R
REF
T
=50:
Min
1.0
1.0
1.0
1.0
1.0
-0.4
DDQ
V
=0.5*V
REF
0.1 + 0.01
0.1 + 0.01
Value
DDQ
128M DDR SDRAM
Max
5.0
4.0
4.0
6.5
6.5
Rev. 2.0 (Jan. 2003)
Unit
V/ns
V
V
V
V
V
Unit
uF
uF
Unit
pF
pF
pF
pF
pF
Note

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