k4d263238a-gc50 Samsung Semiconductor, Inc., k4d263238a-gc50 Datasheet - Page 15

• Manufacturer Part Number: k4d263238a-gc50
• Description: 1m X 32bit X 4 Banks Double Data Rate Synchronous Ram With Bi-directional Data Strobe And Dll
• Manufacturer: Samsung Semiconductor, Inc.

K4D26323RA-GC
tQH Timing (CL4, BL2)
COMMAND
Note 1 :
- A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle
- tQHmin = tHP-X where
- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case
- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data
variation and replaces tDV
. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)
. X=A frequency dependent timing allowance account for tDQSQmax
strobe and all data associated with that data strobe are coincidentally valid.
output vaild window even then the clock duty cycle applied to the device is better than 45/55%
CK, CK
DQS
DQ
CS
READA
0
1
1
* VDD / VDDQ=2.8V *
2
- 15 -
3
tDQSQ(max)
4
Qa0
tQH
tHP
tDQSQ(max)
128M DDR SDRAM
Qa1
Rev. 2.0 (Jan. 2003)
5